Lines Matching +full:value +full:- +full:start
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
5 * Copyright (C) 1996-2000 Russell King
18 #include <asm/asm-bug.h>
19 #include <asm/asm-extable.h>
20 #include <asm/asm-offsets.h>
23 #include <asm/debug-monitors.h>
25 #include <asm/pgtable-hwdef.h>
31 * reference after a 'w' to obtain the 32-bit version.
88 * Value prediction barrier
155 * Define a macro that constructs a 64-bit value by concatenating two
156 * 32-bit registers. Note that on big endian systems the order of the
168 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
169 * <symbol> is within the range +/- 4 GB of the PC.
183 * @tmp: optional 64-bit scratch register to be used if <dst> is a
184 * 32-bit wide register, in which case it cannot be used to hold
200 * @tmp: mandatory 64-bit scratch register to calculate the address
235 * @sym: The name of the per-cpu variable
247 * @sym: The name of the per-cpu variable
257 * read_ctr - read CTR_EL0. If the system has mismatched register fields,
258 * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val
283 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
294 * dcache_line_size - get the safe D-cache line size across all CPUs
304 * raw_icache_line_size - get the minimum I-cache line size on this CPU
315 * icache_line_size - get the safe I-cache line size across all CPUs
325 * tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map
332 * tcr_set_t1sz - update TCR.T1SZ
339 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported
340 * ID_AA64MMFR0_EL1.PARange value
342 * tcr: register with the TCR_ELx value to be updated
371 * [start, end) with dcache line size explicitly provided.
375 * start: starting virtual address of the region
379 * Corrupts: start, end, tmp
381 .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup
383 bic \start, \start, \tmp
386 __dcache_op_workaround_clean_cache \op, \start
389 __dcache_op_workaround_clean_cache \op, \start
392 sys 3, c7, c12, 1, \start // dc cvap
395 sys 3, c7, c13, 1, \start // dc cvadp
397 dc \op, \start
402 add \start, \start, \linesz
403 cmp \start, \end
412 * [start, end)
416 * start: starting virtual address of the region
419 * Corrupts: start, end, tmp1, tmp2
421 .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
423 dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup
428 * [start, end)
430 * start, end: virtual addresses describing the region
434 .macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup
437 bic \tmp2, \start, \tmp2
450 * load_ttbr1 - install @pgtbl as a TTBR1 page table
478 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
491 * reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present
501 * copy_page - copy src to dest using temp registers t1-t8
514 tst \src, #(PAGE_SIZE - 1)
537 * Emit a 64-bit absolute little endian symbol reference in a way that
548 * mov_q - move an immediate constant into a 64-bit register using
575 * If the kernel is built for 52-bit virtual addressing but the hardware only
578 * pgdir entry that covers the lowest 48-bit addressable VA.
580 * Note that this trick is only used for LVA/64k pages - LPA2/4k pages uses an
586 * orr is used as it can cover the immediate value (and is idempotent).
587 * ttbr: Value of ttbr to set, modified.
600 * Arrange a physical address in a TTBR register, taking care of 52-bit
604 * ttbr: returns the TTBR value
625 * tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU.
645 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
654 * frame_push - Push @regcount callee saved registers to the stack,
656 * the new value of sp. Add @extra bytes of stack space
664 * frame_pop - Pop the callee saved registers from the stack that were
690 .if .Lframe_regcount != -1
697 stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]!
708 .if .Lframe_regcount == -1
712 .set .Lframe_regcount, -1
717 * Set SCTLR_ELx to the @reg value, and invalidate the local icache
724 * Invalidate the local I-cache so that any instructions fetched
795 .long 2f - 1f
796 .long 6f - 3f
802 .long 5f - 4f
807 * clang and GCC) treat this as a 32 bit value so no swizzling
846 /* Save/restores x0-x3 to the stack */
849 stp x0, x1, [sp, #-16]!
850 stp x2, x3, [sp, #-16]!