Lines Matching +full:armv8 +full:- +full:based
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Accelerated GHASH implementation with ARMv8 PMULL instructions.
5 * Copyright (C) 2014 - 2018 Linaro Ltd. <ard.biesheuvel@linaro.org>
61 .arch armv8-a+crypto
149 ld1 {HH.2d-HH4.2d}, [x8]
197 // PMULL (64x64->128) based reduction for CPUs that can do
214 // 64x64->128 PMULL instruction
256 1: ld1 {XM3.16b-TT4.16b}, [x2], #64
388 ld1 {K0.4s-K3.4s}, [\rk]
389 ld1 {K4.4s-K5.4s}, [\tmp]
392 ld1 {KK.4s-KM.4s}, [\tmp]
409 ld1 {K6.4s-K7.4s}, [\tmp], #32
426 ld1 {K8.4s-K9.4s}, [\tmp], #32
429 ld1 {K6.4s-K7.4s}, [\tmp]
444 ld1 {HH.2d-HH4.2d}, [x3]
470 ld1 {INP0.16b-INP3.16b}, [x2], #64
500 cmp x0, #-16
502 cmp x0, #-32
504 cmp x0, #-48
524 st1 {INP0.16b-INP3.16b}, [x1], #64
557 mvn XL.16b, XL.16b // -1 for fail, 0 for pass
572 6: ld1 {T1.16b-T2.16b}, [x17], #32 // permute vectors
593 tbl INP3.16b, {INP3.16b}, T1.16b // clear non-data bits
719 ld1 {K6.4s-K7.4s}, [x10], #32
727 ld1 {K8.4s-K9.4s}, [x10], #32
731 ld1 {K6.4s-K7.4s}, [x10]