Lines Matching +full:xlnx +full:- +full:zynqmp +full:- +full:dpdma
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
23 compatible = "xlnx,zynqmp";
24 #address-cells = <2>;
25 #size-cells = <2>;
28 u-boot {
29 compatible = "u-boot,config";
30 bootscr-address = /bits/ 64 <0x20000000>;
35 #address-cells = <1>;
36 #size-cells = <0>;
39 compatible = "arm,cortex-a53";
41 enable-method = "psci";
42 operating-points-v2 = <&cpu_opp_table>;
44 cpu-idle-states = <&CPU_SLEEP_0>;
45 next-level-cache = <&L2>;
49 compatible = "arm,cortex-a53";
51 enable-method = "psci";
53 operating-points-v2 = <&cpu_opp_table>;
54 cpu-idle-states = <&CPU_SLEEP_0>;
55 next-level-cache = <&L2>;
59 compatible = "arm,cortex-a53";
61 enable-method = "psci";
63 operating-points-v2 = <&cpu_opp_table>;
64 cpu-idle-states = <&CPU_SLEEP_0>;
65 next-level-cache = <&L2>;
69 compatible = "arm,cortex-a53";
71 enable-method = "psci";
73 operating-points-v2 = <&cpu_opp_table>;
74 cpu-idle-states = <&CPU_SLEEP_0>;
75 next-level-cache = <&L2>;
78 L2: l2-cache {
80 cache-level = <2>;
81 cache-unified;
84 idle-states {
85 entry-method = "psci";
87 CPU_SLEEP_0: cpu-sleep-0 {
88 compatible = "arm,idle-state";
89 arm,psci-suspend-param = <0x40000000>;
90 local-timer-stop;
91 entry-latency-us = <300>;
92 exit-latency-us = <600>;
93 min-residency-us = <10000>;
98 cpu_opp_table: opp-table-cpu {
99 compatible = "operating-points-v2";
100 opp-shared;
102 opp-hz = /bits/ 64 <1199999988>;
103 opp-microvolt = <1000000>;
104 clock-latency-ns = <500000>;
107 opp-hz = /bits/ 64 <599999994>;
108 opp-microvolt = <1000000>;
109 clock-latency-ns = <500000>;
112 opp-hz = /bits/ 64 <399999996>;
113 opp-microvolt = <1000000>;
114 clock-latency-ns = <500000>;
117 opp-hz = /bits/ 64 <299999997>;
118 opp-microvolt = <1000000>;
119 clock-latency-ns = <500000>;
123 reserved-memory {
124 #address-cells = <2>;
125 #size-cells = <2>;
129 no-map;
134 no-map;
139 zynqmp_ipi: zynqmp-ipi {
140 bootph-all;
141 compatible = "xlnx,zynqmp-ipi-mailbox";
142 interrupt-parent = <&gic>;
144 xlnx,ipi-id = <0>;
145 #address-cells = <2>;
146 #size-cells = <2>;
150 bootph-all;
151 compatible = "xlnx,zynqmp-ipi-dest-mailbox";
156 reg-names = "local_request_region",
160 #mbox-cells = <1>;
161 xlnx,ipi-id = <4>;
168 bootph-all;
172 compatible = "arm,cortex-a53-pmu";
173 interrupt-parent = <&gic>;
178 interrupt-affinity = <&cpu0>,
185 compatible = "arm,psci-0.2";
191 compatible = "linaro,optee-tz";
195 zynqmp_firmware: zynqmp-firmware {
196 compatible = "xlnx,zynqmp-firmware";
197 #power-domain-cells = <1>;
199 bootph-all;
201 zynqmp_power: power-management {
202 bootph-all;
203 compatible = "xlnx,zynqmp-power";
204 interrupt-parent = <&gic>;
207 mbox-names = "tx", "rx";
210 soc-nvmem {
211 compatible = "xlnx,zynqmp-nvmem-fw";
212 nvmem-layout {
213 compatible = "fixed-layout";
214 #address-cells = <1>;
215 #size-cells = <1>;
217 soc_revision: soc-revision@0 {
221 efuse_dna: efuse-dna@c {
224 efuse_usr0: efuse-usr0@20 {
227 efuse_usr1: efuse-usr1@24 {
230 efuse_usr2: efuse-usr2@28 {
233 efuse_usr3: efuse-usr3@2c {
236 efuse_usr4: efuse-usr4@30 {
239 efuse_usr5: efuse-usr5@34 {
242 efuse_usr6: efuse-usr6@38 {
245 efuse_usr7: efuse-usr7@3c {
248 efuse_miscusr: efuse-miscusr@40 {
251 efuse_chash: efuse-chash@50 {
254 efuse_pufmisc: efuse-pufmisc@54 {
257 efuse_sec: efuse-sec@58 {
260 efuse_spkid: efuse-spkid@5c {
263 efuse_aeskey: efuse-aeskey@60 {
266 efuse_ppk0hash: efuse-ppk0hash@a0 {
269 efuse_ppk1hash: efuse-ppk1hash@d0 {
272 efuse_pufuser: efuse-pufuser@100 {
279 compatible = "xlnx,zynqmp-pcap-fpga";
282 xlnx_aes: zynqmp-aes {
283 compatible = "xlnx,zynqmp-aes";
286 zynqmp_reset: reset-controller {
287 compatible = "xlnx,zynqmp-reset";
288 #reset-cells = <1>;
292 compatible = "xlnx,zynqmp-pinctrl";
297 compatible = "xlnx,zynqmp-gpio-modepin";
298 gpio-controller;
299 #gpio-cells = <2>;
305 compatible = "arm,armv8-timer";
306 interrupt-parent = <&gic>;
313 fpga_full: fpga-region {
314 compatible = "fpga-region";
315 fpga-mgr = <&zynqmp_pcap>;
316 #address-cells = <2>;
317 #size-cells = <2>;
322 compatible = "xlnx,zynqmp-r5fss";
323 xlnx,cluster-mode = <1>;
324 xlnx,tcm-mode = <1>;
326 #address-cells = <2>;
327 #size-cells = <2>;
335 compatible = "xlnx,zynqmp-r5f";
340 reg-names = "atcm0", "btcm0", "atcm1", "btcm1";
341 power-domains = <&zynqmp_firmware PD_RPU_0>,
346 memory-region = <&rproc_0_fw_image>;
350 compatible = "xlnx,zynqmp-r5f";
352 reg-names = "atcm0", "btcm0";
353 power-domains = <&zynqmp_firmware PD_RPU_1>,
356 memory-region = <&rproc_1_fw_image>;
360 rproc_split: remoteproc-split@ffe00000 {
362 compatible = "xlnx,zynqmp-r5fss";
363 xlnx,cluster-mode = <0>;
364 xlnx,tcm-mode = <0>;
366 #address-cells = <2>;
367 #size-cells = <2>;
375 compatible = "xlnx,zynqmp-r5f";
377 reg-names = "atcm0", "btcm0";
378 power-domains = <&zynqmp_firmware PD_RPU_0>,
381 memory-region = <&rproc_0_fw_image>;
385 compatible = "xlnx,zynqmp-r5f";
387 reg-names = "atcm0", "btcm0";
388 power-domains = <&zynqmp_firmware PD_RPU_1>,
391 memory-region = <&rproc_1_fw_image>;
396 compatible = "simple-bus";
397 bootph-all;
398 #address-cells = <2>;
399 #size-cells = <2>;
403 compatible = "xlnx,zynq-can-1.0";
405 clock-names = "can_clk", "pclk";
408 interrupt-parent = <&gic>;
409 tx-fifo-depth = <0x40>;
410 rx-fifo-depth = <0x40>;
412 power-domains = <&zynqmp_firmware PD_CAN_0>;
416 compatible = "xlnx,zynq-can-1.0";
418 clock-names = "can_clk", "pclk";
421 interrupt-parent = <&gic>;
422 tx-fifo-depth = <0x40>;
423 rx-fifo-depth = <0x40>;
425 power-domains = <&zynqmp_firmware PD_CAN_1>;
429 compatible = "arm,cci-400";
433 #address-cells = <1>;
434 #size-cells = <1>;
437 compatible = "arm,cci-400-pmu,r1";
439 interrupt-parent = <&gic>;
449 compatible = "arm,coresight-cpu-debug", "arm,primecell";
451 clock-names = "apb_pclk";
456 compatible = "arm,coresight-cpu-debug", "arm,primecell";
458 clock-names = "apb_pclk";
463 compatible = "arm,coresight-cpu-debug", "arm,primecell";
465 clock-names = "apb_pclk";
470 compatible = "arm,coresight-cpu-debug", "arm,primecell";
472 clock-names = "apb_pclk";
477 fpd_dma_chan1: dma-controller@fd500000 {
479 compatible = "xlnx,zynqmp-dma-1.0";
481 interrupt-parent = <&gic>;
483 clock-names = "clk_main", "clk_apb";
484 #dma-cells = <1>;
485 xlnx,bus-width = <128>;
487 power-domains = <&zynqmp_firmware PD_GDMA>;
490 fpd_dma_chan2: dma-controller@fd510000 {
492 compatible = "xlnx,zynqmp-dma-1.0";
494 interrupt-parent = <&gic>;
496 clock-names = "clk_main", "clk_apb";
497 #dma-cells = <1>;
498 xlnx,bus-width = <128>;
500 power-domains = <&zynqmp_firmware PD_GDMA>;
503 fpd_dma_chan3: dma-controller@fd520000 {
505 compatible = "xlnx,zynqmp-dma-1.0";
507 interrupt-parent = <&gic>;
509 clock-names = "clk_main", "clk_apb";
510 #dma-cells = <1>;
511 xlnx,bus-width = <128>;
513 power-domains = <&zynqmp_firmware PD_GDMA>;
516 fpd_dma_chan4: dma-controller@fd530000 {
518 compatible = "xlnx,zynqmp-dma-1.0";
520 interrupt-parent = <&gic>;
522 clock-names = "clk_main", "clk_apb";
523 #dma-cells = <1>;
524 xlnx,bus-width = <128>;
526 power-domains = <&zynqmp_firmware PD_GDMA>;
529 fpd_dma_chan5: dma-controller@fd540000 {
531 compatible = "xlnx,zynqmp-dma-1.0";
533 interrupt-parent = <&gic>;
535 clock-names = "clk_main", "clk_apb";
536 #dma-cells = <1>;
537 xlnx,bus-width = <128>;
539 power-domains = <&zynqmp_firmware PD_GDMA>;
542 fpd_dma_chan6: dma-controller@fd550000 {
544 compatible = "xlnx,zynqmp-dma-1.0";
546 interrupt-parent = <&gic>;
548 clock-names = "clk_main", "clk_apb";
549 #dma-cells = <1>;
550 xlnx,bus-width = <128>;
552 power-domains = <&zynqmp_firmware PD_GDMA>;
555 fpd_dma_chan7: dma-controller@fd560000 {
557 compatible = "xlnx,zynqmp-dma-1.0";
559 interrupt-parent = <&gic>;
561 clock-names = "clk_main", "clk_apb";
562 #dma-cells = <1>;
563 xlnx,bus-width = <128>;
565 power-domains = <&zynqmp_firmware PD_GDMA>;
568 fpd_dma_chan8: dma-controller@fd570000 {
570 compatible = "xlnx,zynqmp-dma-1.0";
572 interrupt-parent = <&gic>;
574 clock-names = "clk_main", "clk_apb";
575 #dma-cells = <1>;
576 xlnx,bus-width = <128>;
578 power-domains = <&zynqmp_firmware PD_GDMA>;
581 gic: interrupt-controller@f9010000 {
582 compatible = "arm,gic-400";
583 #interrupt-cells = <3>;
588 interrupt-controller;
589 interrupt-parent = <&gic>;
595 compatible = "xlnx,zynqmp-mali", "arm,mali-400";
597 interrupt-parent = <&gic>;
604 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
605 clock-names = "bus", "core";
606 power-domains = <&zynqmp_firmware PD_GPU>;
613 lpd_dma_chan1: dma-controller@ffa80000 {
615 compatible = "xlnx,zynqmp-dma-1.0";
617 interrupt-parent = <&gic>;
619 clock-names = "clk_main", "clk_apb";
620 #dma-cells = <1>;
621 xlnx,bus-width = <64>;
623 power-domains = <&zynqmp_firmware PD_ADMA>;
626 lpd_dma_chan2: dma-controller@ffa90000 {
628 compatible = "xlnx,zynqmp-dma-1.0";
630 interrupt-parent = <&gic>;
632 clock-names = "clk_main", "clk_apb";
633 #dma-cells = <1>;
634 xlnx,bus-width = <64>;
636 power-domains = <&zynqmp_firmware PD_ADMA>;
639 lpd_dma_chan3: dma-controller@ffaa0000 {
641 compatible = "xlnx,zynqmp-dma-1.0";
643 interrupt-parent = <&gic>;
645 clock-names = "clk_main", "clk_apb";
646 #dma-cells = <1>;
647 xlnx,bus-width = <64>;
649 power-domains = <&zynqmp_firmware PD_ADMA>;
652 lpd_dma_chan4: dma-controller@ffab0000 {
654 compatible = "xlnx,zynqmp-dma-1.0";
656 interrupt-parent = <&gic>;
658 clock-names = "clk_main", "clk_apb";
659 #dma-cells = <1>;
660 xlnx,bus-width = <64>;
662 power-domains = <&zynqmp_firmware PD_ADMA>;
665 lpd_dma_chan5: dma-controller@ffac0000 {
667 compatible = "xlnx,zynqmp-dma-1.0";
669 interrupt-parent = <&gic>;
671 clock-names = "clk_main", "clk_apb";
672 #dma-cells = <1>;
673 xlnx,bus-width = <64>;
675 power-domains = <&zynqmp_firmware PD_ADMA>;
678 lpd_dma_chan6: dma-controller@ffad0000 {
680 compatible = "xlnx,zynqmp-dma-1.0";
682 interrupt-parent = <&gic>;
684 clock-names = "clk_main", "clk_apb";
685 #dma-cells = <1>;
686 xlnx,bus-width = <64>;
688 power-domains = <&zynqmp_firmware PD_ADMA>;
691 lpd_dma_chan7: dma-controller@ffae0000 {
693 compatible = "xlnx,zynqmp-dma-1.0";
695 interrupt-parent = <&gic>;
697 clock-names = "clk_main", "clk_apb";
698 #dma-cells = <1>;
699 xlnx,bus-width = <64>;
701 power-domains = <&zynqmp_firmware PD_ADMA>;
704 lpd_dma_chan8: dma-controller@ffaf0000 {
706 compatible = "xlnx,zynqmp-dma-1.0";
708 interrupt-parent = <&gic>;
710 clock-names = "clk_main", "clk_apb";
711 #dma-cells = <1>;
712 xlnx,bus-width = <64>;
714 power-domains = <&zynqmp_firmware PD_ADMA>;
717 mc: memory-controller@fd070000 {
718 compatible = "xlnx,zynqmp-ddrc-2.40a";
720 interrupt-parent = <&gic>;
724 nand0: nand-controller@ff100000 {
725 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
728 clock-names = "controller", "bus";
729 interrupt-parent = <&gic>;
731 #address-cells = <1>;
732 #size-cells = <0>;
734 power-domains = <&zynqmp_firmware PD_NAND>;
738 compatible = "xlnx,zynqmp-gem", "cdns,gem";
740 interrupt-parent = <&gic>;
744 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
746 power-domains = <&zynqmp_firmware PD_ETH_0>;
748 reset-names = "gem0_rst";
752 compatible = "xlnx,zynqmp-gem", "cdns,gem";
754 interrupt-parent = <&gic>;
758 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
760 power-domains = <&zynqmp_firmware PD_ETH_1>;
762 reset-names = "gem1_rst";
766 compatible = "xlnx,zynqmp-gem", "cdns,gem";
768 interrupt-parent = <&gic>;
772 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
774 power-domains = <&zynqmp_firmware PD_ETH_2>;
776 reset-names = "gem2_rst";
780 compatible = "xlnx,zynqmp-gem", "cdns,gem";
782 interrupt-parent = <&gic>;
786 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
788 power-domains = <&zynqmp_firmware PD_ETH_3>;
790 reset-names = "gem3_rst";
794 compatible = "xlnx,zynqmp-gpio-1.0";
796 #gpio-cells = <0x2>;
797 gpio-controller;
798 interrupt-parent = <&gic>;
800 interrupt-controller;
801 #interrupt-cells = <2>;
803 power-domains = <&zynqmp_firmware PD_GPIO>;
807 compatible = "cdns,i2c-r1p14";
809 interrupt-parent = <&gic>;
811 clock-frequency = <400000>;
813 #address-cells = <1>;
814 #size-cells = <0>;
815 power-domains = <&zynqmp_firmware PD_I2C_0>;
819 compatible = "cdns,i2c-r1p14";
821 interrupt-parent = <&gic>;
823 clock-frequency = <400000>;
825 #address-cells = <1>;
826 #size-cells = <0>;
827 power-domains = <&zynqmp_firmware PD_I2C_1>;
830 ocm: memory-controller@ff960000 {
831 compatible = "xlnx,zynqmp-ocmc-1.0";
833 interrupt-parent = <&gic>;
838 compatible = "xlnx,nwl-pcie-2.11";
840 #address-cells = <3>;
841 #size-cells = <2>;
842 #interrupt-cells = <1>;
843 msi-controller;
845 interrupt-parent = <&gic>;
851 interrupt-names = "misc", "dummy", "intx",
853 msi-parent = <&pcie>;
857 reg-names = "breg", "pcireg", "cfg";
858 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-pre…
860 bus-range = <0x00 0xff>;
861 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
862 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
867 power-domains = <&zynqmp_firmware PD_PCIE>;
868 pcie_intc: legacy-interrupt-controller {
869 interrupt-controller;
870 #address-cells = <0>;
871 #interrupt-cells = <1>;
876 bootph-all;
877 compatible = "xlnx,zynqmp-qspi-1.0";
879 clock-names = "ref_clk", "pclk";
881 interrupt-parent = <&gic>;
882 num-cs = <1>;
885 #address-cells = <1>;
886 #size-cells = <0>;
888 power-domains = <&zynqmp_firmware PD_QSPI>;
892 compatible = "xlnx,zynqmp-psgtr-v1.1";
896 reg-names = "serdes", "siou";
897 #phy-cells = <4>;
901 compatible = "xlnx,zynqmp-rtc";
904 interrupt-parent = <&gic>;
907 interrupt-names = "alarm", "sec";
912 compatible = "ceva,ahci-1v84";
915 interrupt-parent = <&gic>;
917 power-domains = <&zynqmp_firmware PD_SATA>;
923 bootph-all;
924 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
926 interrupt-parent = <&gic>;
929 clock-names = "clk_xin", "clk_ahb";
931 #clock-cells = <1>;
932 clock-output-names = "clk_out_sd0", "clk_in_sd0";
933 power-domains = <&zynqmp_firmware PD_SD_0>;
938 bootph-all;
939 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
941 interrupt-parent = <&gic>;
944 clock-names = "clk_xin", "clk_ahb";
946 #clock-cells = <1>;
947 clock-output-names = "clk_out_sd1", "clk_in_sd1";
948 power-domains = <&zynqmp_firmware PD_SD_1>;
953 compatible = "arm,mmu-500";
955 #iommu-cells = <1>;
957 #global-interrupts = <1>;
958 interrupt-parent = <&gic>;
979 compatible = "cdns,spi-r1p6";
981 interrupt-parent = <&gic>;
984 clock-names = "ref_clk", "pclk";
985 #address-cells = <1>;
986 #size-cells = <0>;
987 power-domains = <&zynqmp_firmware PD_SPI_0>;
991 compatible = "cdns,spi-r1p6";
993 interrupt-parent = <&gic>;
996 clock-names = "ref_clk", "pclk";
997 #address-cells = <1>;
998 #size-cells = <0>;
999 power-domains = <&zynqmp_firmware PD_SPI_1>;
1005 interrupt-parent = <&gic>;
1010 timer-width = <32>;
1011 power-domains = <&zynqmp_firmware PD_TTC_0>;
1017 interrupt-parent = <&gic>;
1022 timer-width = <32>;
1023 power-domains = <&zynqmp_firmware PD_TTC_1>;
1029 interrupt-parent = <&gic>;
1034 timer-width = <32>;
1035 power-domains = <&zynqmp_firmware PD_TTC_2>;
1041 interrupt-parent = <&gic>;
1046 timer-width = <32>;
1047 power-domains = <&zynqmp_firmware PD_TTC_3>;
1051 bootph-all;
1052 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
1054 interrupt-parent = <&gic>;
1057 clock-names = "uart_clk", "pclk";
1058 power-domains = <&zynqmp_firmware PD_UART_0>;
1063 bootph-all;
1064 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
1066 interrupt-parent = <&gic>;
1069 clock-names = "uart_clk", "pclk";
1070 power-domains = <&zynqmp_firmware PD_UART_1>;
1075 #address-cells = <2>;
1076 #size-cells = <2>;
1078 compatible = "xlnx,zynqmp-dwc3";
1080 clock-names = "bus_clk", "ref_clk";
1081 power-domains = <&zynqmp_firmware PD_USB_0>;
1085 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
1086 reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
1093 interrupt-parent = <&gic>;
1094 interrupt-names = "host", "peripheral", "otg", "wakeup";
1099 clock-names = "ref";
1101 snps,quirk-frame-length-adjustment = <0x20>;
1102 snps,resume-hs-terminations;
1103 /* dma-coherent; */
1108 #address-cells = <2>;
1109 #size-cells = <2>;
1111 compatible = "xlnx,zynqmp-dwc3";
1113 clock-names = "bus_clk", "ref_clk";
1114 power-domains = <&zynqmp_firmware PD_USB_1>;
1118 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
1125 interrupt-parent = <&gic>;
1126 interrupt-names = "host", "peripheral", "otg", "wakeup";
1131 clock-names = "ref";
1133 snps,quirk-frame-length-adjustment = <0x20>;
1134 snps,resume-hs-terminations;
1135 /* dma-coherent; */
1140 compatible = "cdns,wdt-r1p2";
1142 interrupt-parent = <&gic>;
1145 timeout-sec = <60>;
1146 reset-on-timeout;
1150 compatible = "cdns,wdt-r1p2";
1152 interrupt-parent = <&gic>;
1155 timeout-sec = <10>;
1159 compatible = "xlnx,zynqmp-ams";
1161 interrupt-parent = <&gic>;
1164 #address-cells = <1>;
1165 #size-cells = <1>;
1166 #io-channel-cells = <1>;
1169 ams_ps: ams-ps@0 {
1170 compatible = "xlnx,zynqmp-ams-ps";
1175 ams_pl: ams-pl@400 {
1176 compatible = "xlnx,zynqmp-ams-pl";
1182 zynqmp_dpdma: dma-controller@fd4c0000 {
1183 compatible = "xlnx,zynqmp-dpdma";
1187 interrupt-parent = <&gic>;
1188 clock-names = "axi_clk";
1189 power-domains = <&zynqmp_firmware PD_DP>;
1191 #dma-cells = <1>;
1195 bootph-all;
1196 compatible = "xlnx,zynqmp-dpsub-1.7";
1202 reg-names = "dp", "blend", "av_buf", "aud";
1204 interrupt-parent = <&gic>;
1206 clock-names = "dp_apb_clk", "dp_aud_clk",
1208 power-domains = <&zynqmp_firmware PD_DP>;
1210 dma-names = "vid0", "vid1", "vid2", "gfx0";
1217 #address-cells = <1>;
1218 #size-cells = <0>;