Lines Matching +full:0 +full:xff9905c0
30 bootscr-address = /bits/ 64 <0x20000000>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
43 reg = <0x0>;
52 reg = <0x1>;
62 reg = <0x2>;
72 reg = <0x3>;
87 CPU_SLEEP_0: cpu-sleep-0 {
89 arm,psci-suspend-param = <0x40000000>;
130 reg = <0x0 0x3ed00000 0x0 0x40000>;
135 reg = <0x0 0x3ef00000 0x0 0x40000>;
144 xlnx,ipi-id = <0>;
152 reg = <0x0 0xff9905c0 0x0 0x20>,
153 <0x0 0xff9905e0 0x0 0x20>,
154 <0x0 0xff990e80 0x0 0x20>,
155 <0x0 0xff990ea0 0x0 0x20>;
206 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
217 soc_revision: soc-revision@0 {
218 reg = <0x0 0x4>;
222 reg = <0xc 0xc>;
225 reg = <0x20 0x4>;
228 reg = <0x24 0x4>;
231 reg = <0x28 0x4>;
234 reg = <0x2c 0x4>;
237 reg = <0x30 0x4>;
240 reg = <0x34 0x4>;
243 reg = <0x38 0x4>;
246 reg = <0x3c 0x4>;
249 reg = <0x40 0x4>;
252 reg = <0x50 0x4>;
255 reg = <0x54 0x4>;
258 reg = <0x58 0x4>;
261 reg = <0x5c 0x4>;
264 reg = <0x60 0x20>;
267 reg = <0xa0 0x30>;
270 reg = <0xd0 0x30>;
273 reg = <0x100 0x7F>;
329 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
330 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
331 <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>,
332 <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>;
334 r5f@0 {
336 reg = <0x0 0x0 0x0 0x10000>,
337 <0x0 0x20000 0x0 0x10000>,
338 <0x0 0x10000 0x0 0x10000>,
339 <0x0 0x30000 0x0 0x10000>;
351 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
363 xlnx,cluster-mode = <0>;
364 xlnx,tcm-mode = <0>;
369 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
370 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
371 <0x1 0x0 0x0 0xffe90000 0x0 0x10000>,
372 <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>;
374 r5f@0 {
376 reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>;
386 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
406 reg = <0x0 0xff060000 0x0 0x1000>;
409 tx-fifo-depth = <0x40>;
410 rx-fifo-depth = <0x40>;
419 reg = <0x0 0xff070000 0x0 0x1000>;
422 tx-fifo-depth = <0x40>;
423 rx-fifo-depth = <0x40>;
431 reg = <0x0 0xfd6e0000 0x0 0x9000>;
432 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
438 reg = <0x9000 0x5000>;
450 reg = <0x0 0xfec10000 0x0 0x1000>;
457 reg = <0x0 0xfed10000 0x0 0x1000>;
464 reg = <0x0 0xfee10000 0x0 0x1000>;
471 reg = <0x0 0xfef10000 0x0 0x1000>;
480 reg = <0x0 0xfd500000 0x0 0x1000>;
486 /* iommus = <&smmu 0x14e8>; */
493 reg = <0x0 0xfd510000 0x0 0x1000>;
499 /* iommus = <&smmu 0x14e9>; */
506 reg = <0x0 0xfd520000 0x0 0x1000>;
512 /* iommus = <&smmu 0x14ea>; */
519 reg = <0x0 0xfd530000 0x0 0x1000>;
525 /* iommus = <&smmu 0x14eb>; */
532 reg = <0x0 0xfd540000 0x0 0x1000>;
538 /* iommus = <&smmu 0x14ec>; */
545 reg = <0x0 0xfd550000 0x0 0x1000>;
551 /* iommus = <&smmu 0x14ed>; */
558 reg = <0x0 0xfd560000 0x0 0x1000>;
564 /* iommus = <&smmu 0x14ee>; */
571 reg = <0x0 0xfd570000 0x0 0x1000>;
577 /* iommus = <&smmu 0x14ef>; */
584 reg = <0x0 0xf9010000 0x0 0x10000>,
585 <0x0 0xf9020000 0x0 0x20000>,
586 <0x0 0xf9040000 0x0 0x20000>,
587 <0x0 0xf9060000 0x0 0x20000>;
596 reg = <0x0 0xfd4b0000 0x0 0x10000>;
616 reg = <0x0 0xffa80000 0x0 0x1000>;
622 /* iommus = <&smmu 0x868>; */
629 reg = <0x0 0xffa90000 0x0 0x1000>;
635 /* iommus = <&smmu 0x869>; */
642 reg = <0x0 0xffaa0000 0x0 0x1000>;
648 /* iommus = <&smmu 0x86a>; */
655 reg = <0x0 0xffab0000 0x0 0x1000>;
661 /* iommus = <&smmu 0x86b>; */
668 reg = <0x0 0xffac0000 0x0 0x1000>;
674 /* iommus = <&smmu 0x86c>; */
681 reg = <0x0 0xffad0000 0x0 0x1000>;
687 /* iommus = <&smmu 0x86d>; */
694 reg = <0x0 0xffae0000 0x0 0x1000>;
700 /* iommus = <&smmu 0x86e>; */
707 reg = <0x0 0xffaf0000 0x0 0x1000>;
713 /* iommus = <&smmu 0x86f>; */
719 reg = <0x0 0xfd070000 0x0 0x30000>;
727 reg = <0x0 0xff100000 0x0 0x1000>;
732 #size-cells = <0>;
733 /* iommus = <&smmu 0x872>; */
743 reg = <0x0 0xff0b0000 0x0 0x1000>;
745 /* iommus = <&smmu 0x874>; */
757 reg = <0x0 0xff0c0000 0x0 0x1000>;
759 /* iommus = <&smmu 0x875>; */
771 reg = <0x0 0xff0d0000 0x0 0x1000>;
773 /* iommus = <&smmu 0x876>; */
785 reg = <0x0 0xff0e0000 0x0 0x1000>;
787 /* iommus = <&smmu 0x877>; */
796 #gpio-cells = <0x2>;
802 reg = <0x0 0xff0a0000 0x0 0x1000>;
812 reg = <0x0 0xff020000 0x0 0x1000>;
814 #size-cells = <0>;
824 reg = <0x0 0xff030000 0x0 0x1000>;
826 #size-cells = <0>;
832 reg = <0x0 0xff960000 0x0 0x1000>;
850 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */
854 reg = <0x0 0xfd0e0000 0x0 0x1000>,
855 <0x0 0xfd480000 0x0 0x1000>,
856 <0x80 0x00000000 0x0 0x10000000>;
858 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-pre…
859 …<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable mem…
860 bus-range = <0x00 0xff>;
861 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
862 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
863 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
864 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
865 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
866 /* iommus = <&smmu 0x4d0>; */
870 #address-cells = <0>;
883 reg = <0x0 0xff0f0000 0x0 0x1000>,
884 <0x0 0xc0000000 0x0 0x8000000>;
886 #size-cells = <0>;
887 /* iommus = <&smmu 0x873>; */
894 reg = <0x0 0xfd400000 0x0 0x40000>,
895 <0x0 0xfd3d0000 0x0 0x1000>;
903 reg = <0x0 0xffa60000 0x0 0x100>;
908 calibration = <0x7FFF>;
914 reg = <0x0 0xfd0c0000 0x0 0x2000>;
919 /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
928 reg = <0x0 0xff160000 0x0 0x1000>;
930 /* iommus = <&smmu 0x870>; */
943 reg = <0x0 0xff170000 0x0 0x1000>;
945 /* iommus = <&smmu 0x871>; */
954 reg = <0x0 0xfd800000 0x0 0x20000>;
983 reg = <0x0 0xff040000 0x0 0x1000>;
986 #size-cells = <0>;
995 reg = <0x0 0xff050000 0x0 0x1000>;
998 #size-cells = <0>;
1009 reg = <0x0 0xff110000 0x0 0x1000>;
1021 reg = <0x0 0xff120000 0x0 0x1000>;
1033 reg = <0x0 0xff130000 0x0 0x1000>;
1045 reg = <0x0 0xff140000 0x0 0x1000>;
1056 reg = <0x0 0xff000000 0x0 0x1000>;
1068 reg = <0x0 0xff010000 0x0 0x1000>;
1079 reg = <0x0 0xff9d0000 0x0 0x100>;
1092 reg = <0x0 0xfe200000 0x0 0x40000>;
1100 /* iommus = <&smmu 0x860>; */
1101 snps,quirk-frame-length-adjustment = <0x20>;
1112 reg = <0x0 0xff9e0000 0x0 0x100>;
1124 reg = <0x0 0xfe300000 0x0 0x40000>;
1132 /* iommus = <&smmu 0x861>; */
1133 snps,quirk-frame-length-adjustment = <0x20>;
1144 reg = <0x0 0xfd4d0000 0x0 0x1000>;
1154 reg = <0x0 0xff150000 0x0 0x1000>;
1163 reg = <0x0 0xffa50000 0x0 0x800>;
1167 ranges = <0 0 0xffa50800 0x800>;
1169 ams_ps: ams-ps@0 {
1172 reg = <0x0 0x400>;
1178 reg = <0x400 0x400>;
1185 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1190 /* iommus = <&smmu 0xce4>; */
1198 reg = <0x0 0xfd4a0000 0x0 0x1000>,
1199 <0x0 0xfd4aa000 0x0 0x1000>,
1200 <0x0 0xfd4ab000 0x0 0x1000>,
1201 <0x0 0xfd4ac000 0x0 0x1000>;
1205 /* iommus = <&smmu 0xce3>; */
1218 #size-cells = <0>;
1220 port@0 {
1221 reg = <0>;