Lines Matching +full:io +full:- +full:channel +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
40 stdout-path = "serial0:115200n8";
48 gpio-keys {
49 compatible = "gpio-keys";
51 switch-19 {
55 wakeup-source;
61 compatible = "gpio-leds";
62 heartbeat-led {
65 linux,default-trigger = "heartbeat";
69 ina226-u76 {
70 compatible = "iio-hwmon";
71 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
73 ina226-u77 {
74 compatible = "iio-hwmon";
75 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
77 ina226-u78 {
78 compatible = "iio-hwmon";
79 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
81 ina226-u87 {
82 compatible = "iio-hwmon";
83 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
85 ina226-u85 {
86 compatible = "iio-hwmon";
87 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
89 ina226-u86 {
90 compatible = "iio-hwmon";
91 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
93 ina226-u93 {
94 compatible = "iio-hwmon";
95 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
97 ina226-u88 {
98 compatible = "iio-hwmon";
99 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
101 ina226-u15 {
102 compatible = "iio-hwmon";
103 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
105 ina226-u92 {
106 compatible = "iio-hwmon";
107 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
109 ina226-u79 {
110 compatible = "iio-hwmon";
111 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
113 ina226-u81 {
114 compatible = "iio-hwmon";
115 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
117 ina226-u80 {
118 compatible = "iio-hwmon";
119 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
121 ina226-u84 {
122 compatible = "iio-hwmon";
123 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
125 ina226-u16 {
126 compatible = "iio-hwmon";
127 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
129 ina226-u65 {
130 compatible = "iio-hwmon";
131 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
133 ina226-u74 {
134 compatible = "iio-hwmon";
135 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
137 ina226-u75 {
138 compatible = "iio-hwmon";
139 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
144 compatible = "fixed-clock";
145 #clock-cells = <0>;
146 clock-frequency = <48000000>;
150 compatible = "fixed-clock";
151 #clock-cells = <0>;
152 clock-frequency = <114285000>;
156 compatible = "dp-connector";
158 type = "full-size";
162 remote-endpoint = <&dpsub_dp_out>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_can1_default>;
212 phy-handle = <&phy0>;
213 phy-mode = "rgmii-id";
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_gem3_default>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 phy0: ethernet-phy@c {
220 #phy-cells = <1>;
222 compatible = "ethernet-phy-id2000.a231";
223 ti,rx-internal-delay = <0x8>;
224 ti,tx-internal-delay = <0xa>;
225 ti,fifo-depth = <0x1>;
226 ti,dp83867-rxctrl-strap-quirk;
227 reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_gpio_default>;
244 clock-frequency = <400000>;
245 pinctrl-names = "default", "gpio";
246 pinctrl-0 = <&pinctrl_i2c0_default>;
247 pinctrl-1 = <&pinctrl_i2c0_gpio>;
248 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
249 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
254 gpio-controller; /* interrupt not connected */
255 #gpio-cells = <2>;
259 * 0 - SFP_SI5328_INT_ALM
260 * 1 - HDMI_SI5328_INT_ALM
261 * 5 - IIC_MUX_RESET_B
262 * 6 - GEM3_EXP_RESET_B
263 * 10 - FMC_HPC0_PRSNT_M2C_B
264 * 11 - FMC_HPC1_PRSNT_M2C_B
265 * 2-4, 7, 12-17 - not connected
272 gpio-controller;
273 #gpio-cells = <2>;
277 * 0 - VCCPSPLL_EN
278 * 1 - MGTRAVCC_EN
279 * 2 - MGTRAVTT_EN
280 * 3 - VCCPSDDRPLL_EN
281 * 4 - MIO26_PMU_INPUT_LS
282 * 5 - PL_PMBUS_ALERT
283 * 6 - PS_PMBUS_ALERT
284 * 7 - MAXIM_PMBUS_ALERT
285 * 10 - PL_DDR4_VTERM_EN
286 * 11 - PL_DDR4_VPP_2V5_EN
287 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
288 * 13 - PS_DIMM_SUSPEND_EN
289 * 14 - PS_DDR4_VTERM_EN
290 * 15 - PS_DDR4_VPP_2V5_EN
291 * 16 - 17 - not connected
295 i2c-mux@75 { /* u60 */
297 #address-cells = <1>;
298 #size-cells = <0>;
301 #address-cells = <1>;
302 #size-cells = <0>;
307 #io-channel-cells = <1>;
308 label = "ina226-u76";
310 shunt-resistor = <5000>;
314 #io-channel-cells = <1>;
315 label = "ina226-u77";
317 shunt-resistor = <5000>;
321 #io-channel-cells = <1>;
322 label = "ina226-u78";
324 shunt-resistor = <5000>;
328 #io-channel-cells = <1>;
329 label = "ina226-u87";
331 shunt-resistor = <5000>;
335 #io-channel-cells = <1>;
336 label = "ina226-u85";
338 shunt-resistor = <5000>;
342 #io-channel-cells = <1>;
343 label = "ina226-u86";
345 shunt-resistor = <5000>;
349 #io-channel-cells = <1>;
350 label = "ina226-u93";
352 shunt-resistor = <5000>;
356 #io-channel-cells = <1>;
357 label = "ina226-u88";
359 shunt-resistor = <5000>;
363 #io-channel-cells = <1>;
364 label = "ina226-u15";
366 shunt-resistor = <5000>;
370 #io-channel-cells = <1>;
371 label = "ina226-u92";
373 shunt-resistor = <5000>;
377 #address-cells = <1>;
378 #size-cells = <0>;
383 #io-channel-cells = <1>;
384 label = "ina226-u79";
386 shunt-resistor = <2000>;
390 #io-channel-cells = <1>;
391 label = "ina226-u81";
393 shunt-resistor = <5000>;
397 #io-channel-cells = <1>;
398 label = "ina226-u80";
400 shunt-resistor = <5000>;
404 #io-channel-cells = <1>;
405 label = "ina226-u84";
407 shunt-resistor = <5000>;
411 #io-channel-cells = <1>;
412 label = "ina226-u16";
414 shunt-resistor = <5000>;
418 #io-channel-cells = <1>;
419 label = "ina226-u65";
421 shunt-resistor = <5000>;
425 #io-channel-cells = <1>;
426 label = "ina226-u74";
428 shunt-resistor = <5000>;
432 #io-channel-cells = <1>;
433 label = "ina226-u75";
435 shunt-resistor = <5000>;
439 #address-cells = <1>;
440 #size-cells = <0>;
442 /* MAXIM_PMBUS - 00 */
507 clock-frequency = <400000>;
508 pinctrl-names = "default", "gpio";
509 pinctrl-0 = <&pinctrl_i2c1_default>;
510 pinctrl-1 = <&pinctrl_i2c1_gpio>;
511 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
512 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
514 /* PL i2c via PCA9306 - u45 */
515 i2c-mux@74 { /* u34 */
517 #address-cells = <1>;
518 #size-cells = <0>;
521 #address-cells = <1>;
522 #size-cells = <0>;
527 * 0 - 256B address 0x54
528 * 256B - 512B address 0x55
529 * 512B - 768B address 0x56
530 * 768B - 1024B address 0x57
538 #address-cells = <1>;
539 #size-cells = <0>;
541 si5341: clock-generator@36 { /* SI5341 - u69 */
544 #clock-cells = <2>;
545 #address-cells = <1>;
546 #size-cells = <0>;
548 clock-names = "xtal";
549 clock-output-names = "si5341";
552 /* refclk0 for PS-GT, used for DP */
554 always-on;
557 /* refclk2 for PS-GT, used for USB3 */
559 always-on;
562 /* refclk3 for PS-GT, used for SATA */
564 always-on;
569 always-on;
574 always-on;
579 always-on;
585 #address-cells = <1>;
586 #size-cells = <0>;
588 si570_1: clock-generator@5d { /* USER SI570 - u42 */
589 #clock-cells = <0>;
592 temperature-stability = <50>;
593 factory-fout = <300000000>;
594 clock-frequency = <300000000>;
595 clock-output-names = "si570_user";
599 #address-cells = <1>;
600 #size-cells = <0>;
602 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
603 #clock-cells = <0>;
606 temperature-stability = <50>; /* copy from zc702 */
607 factory-fout = <156250000>;
608 clock-frequency = <156250000>;
609 clock-output-names = "si570_mgt";
613 #address-cells = <1>;
614 #size-cells = <0>;
616 /* SI5328 - u20 */
619 #address-cells = <1>;
620 #size-cells = <0>;
622 temp@4c {/* lm96163 - u128 */
627 /* 6 - 7 unconnected */
630 i2c-mux@75 {
632 #address-cells = <1>;
633 #size-cells = <0>;
637 #address-cells = <1>;
638 #size-cells = <0>;
643 #address-cells = <1>;
644 #size-cells = <0>;
649 #address-cells = <1>;
650 #size-cells = <0>;
655 #address-cells = <1>;
656 #size-cells = <0>;
661 #address-cells = <1>;
662 #size-cells = <0>;
667 #address-cells = <1>;
668 #size-cells = <0>;
673 #address-cells = <1>;
674 #size-cells = <0>;
679 #address-cells = <1>;
680 #size-cells = <0>;
689 pinctrl_i2c0_default: i2c0-default {
690 mux {
697 bias-pull-up;
698 slew-rate = <SLEW_RATE_SLOW>;
699 power-source = <IO_STANDARD_LVCMOS18>;
703 pinctrl_i2c0_gpio: i2c0-gpio-grp {
704 mux {
711 slew-rate = <SLEW_RATE_SLOW>;
712 power-source = <IO_STANDARD_LVCMOS18>;
716 pinctrl_i2c1_default: i2c1-default {
717 mux {
724 bias-pull-up;
725 slew-rate = <SLEW_RATE_SLOW>;
726 power-source = <IO_STANDARD_LVCMOS18>;
730 pinctrl_i2c1_gpio: i2c1-gpio-grp {
731 mux {
738 slew-rate = <SLEW_RATE_SLOW>;
739 power-source = <IO_STANDARD_LVCMOS18>;
743 pinctrl_uart0_default: uart0-default {
744 mux {
751 slew-rate = <SLEW_RATE_SLOW>;
752 power-source = <IO_STANDARD_LVCMOS18>;
755 conf-rx {
757 bias-high-impedance;
760 conf-tx {
762 bias-disable;
766 pinctrl_uart1_default: uart1-default {
767 mux {
774 slew-rate = <SLEW_RATE_SLOW>;
775 power-source = <IO_STANDARD_LVCMOS18>;
778 conf-rx {
780 bias-high-impedance;
783 conf-tx {
785 bias-disable;
789 pinctrl_usb0_default: usb0-default {
790 mux {
797 power-source = <IO_STANDARD_LVCMOS18>;
800 conf-rx {
802 bias-high-impedance;
803 drive-strength = <12>;
804 slew-rate = <SLEW_RATE_FAST>;
807 conf-tx {
810 bias-disable;
811 drive-strength = <4>;
812 slew-rate = <SLEW_RATE_SLOW>;
816 pinctrl_gem3_default: gem3-default {
817 mux {
824 slew-rate = <SLEW_RATE_SLOW>;
825 power-source = <IO_STANDARD_LVCMOS18>;
828 conf-rx {
831 bias-high-impedance;
832 low-power-disable;
835 conf-tx {
838 bias-disable;
839 low-power-enable;
842 mux-mdio {
847 conf-mdio {
849 slew-rate = <SLEW_RATE_SLOW>;
850 power-source = <IO_STANDARD_LVCMOS18>;
851 bias-disable;
855 pinctrl_can1_default: can1-default {
856 mux {
863 slew-rate = <SLEW_RATE_SLOW>;
864 power-source = <IO_STANDARD_LVCMOS18>;
867 conf-rx {
869 bias-high-impedance;
872 conf-tx {
874 bias-disable;
878 pinctrl_sdhci1_default: sdhci1-default {
879 mux {
886 slew-rate = <SLEW_RATE_SLOW>;
887 power-source = <IO_STANDARD_LVCMOS18>;
888 bias-disable;
891 mux-cd {
896 conf-cd {
898 bias-high-impedance;
899 bias-pull-up;
900 slew-rate = <SLEW_RATE_SLOW>;
901 power-source = <IO_STANDARD_LVCMOS18>;
904 mux-wp {
909 conf-wp {
911 bias-high-impedance;
912 bias-pull-up;
913 slew-rate = <SLEW_RATE_SLOW>;
914 power-source = <IO_STANDARD_LVCMOS18>;
918 pinctrl_gpio_default: gpio-default {
919 mux {
926 slew-rate = <SLEW_RATE_SLOW>;
927 power-source = <IO_STANDARD_LVCMOS18>;
930 mux-msp {
935 conf-msp {
937 slew-rate = <SLEW_RATE_SLOW>;
938 power-source = <IO_STANDARD_LVCMOS18>;
941 conf-pull-up {
943 bias-pull-up;
946 conf-pull-none {
948 bias-disable;
957 clock-names = "ref1", "ref2", "ref3";
963 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
964 #address-cells = <1>;
965 #size-cells = <1>;
967 spi-tx-bus-width = <4>;
968 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
969 spi-max-frequency = <108000000>; /* Based on DC1 spec */
980 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
981 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
982 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
983 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
984 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
985 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
986 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
987 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
988 phy-names = "sata-phy";
998 no-1-8-v;
999 pinctrl-names = "default";
1000 pinctrl-0 = <&pinctrl_sdhci1_default>;
1001 xlnx,mio-bank = <1>;
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&pinctrl_uart0_default>;
1012 pinctrl-names = "default";
1013 pinctrl-0 = <&pinctrl_uart1_default>;
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&pinctrl_usb0_default>;
1021 phy-names = "usb3-phy";
1029 maximum-speed = "super-speed";
1042 phy-names = "dp-phy0", "dp-phy1";
1049 remote-endpoint = <&dpcon_in>;