Lines Matching +full:p1 +full:- +full:cominit +full:- +full:params
1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
47 compatible = "iio-hwmon";
48 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <125000000>;
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <26000000>;
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <27000000>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_can1_default>;
114 phy-handle = <&phy0>;
115 phy-mode = "rgmii-id";
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_gem3_default>;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 phy0: ethernet-phy@c {
122 #phy-cells = <1>;
123 compatible = "ethernet-phy-id2000.a231";
125 ti,rx-internal-delay = <0x8>;
126 ti,tx-internal-delay = <0xa>;
127 ti,fifo-depth = <0x1>;
128 ti,dp83867-rxctrl-strap-quirk;
129 reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
144 clock-frequency = <400000>;
145 pinctrl-names = "default", "gpio";
146 pinctrl-0 = <&pinctrl_i2c1_default>;
147 pinctrl-1 = <&pinctrl_i2c1_gpio>;
148 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
149 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
154 gpio-controller;
155 #gpio-cells = <2>;
159 * 0 - IRPS5401_ALERT_B
160 * 1 - HDMI_8T49N241_INT_ALM
161 * 2 - MAX6643_OT_B
162 * 3 - MAX6643_FANFAIL_B
163 * 5 - IIC_MUX_RESET_B
164 * 6 - GEM3_EXP_RESET_B
165 * 7 - FMC_LPC_PRSNT_M2C_B
166 * 4, 10 - 17 - not connected
170 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
171 i2c-mux@74 { /* u34 */
173 #address-cells = <1>;
174 #size-cells = <0>;
177 #address-cells = <1>;
178 #size-cells = <0>;
183 * 0 - 256B address 0x54
184 * 256B - 512B address 0x55
185 * 512B - 768B address 0x56
186 * 768B - 1024B address 0x57
191 #address-cells = <1>;
192 #size-cells = <1>;
197 #address-cells = <1>;
198 #size-cells = <0>;
200 /* 8T49N287 - u182 */
204 #address-cells = <1>;
205 #size-cells = <0>;
207 irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
211 irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
218 #address-cells = <1>;
219 #size-cells = <0>;
223 #io-channel-cells = <1>;
225 shunt-resistor = <5000>;
230 #address-cells = <1>;
231 #size-cells = <0>;
236 #address-cells = <1>;
237 #size-cells = <0>;
248 pinctrl_can1_default: can1-default {
256 slew-rate = <SLEW_RATE_SLOW>;
257 power-source = <IO_STANDARD_LVCMOS18>;
258 drive-strength = <12>;
261 conf-rx {
263 bias-high-impedance;
266 conf-tx {
268 bias-disable;
272 pinctrl_i2c1_default: i2c1-default {
280 bias-pull-up;
281 slew-rate = <SLEW_RATE_SLOW>;
282 power-source = <IO_STANDARD_LVCMOS18>;
283 drive-strength = <12>;
287 pinctrl_i2c1_gpio: i2c1-gpio-grp {
295 slew-rate = <SLEW_RATE_SLOW>;
296 power-source = <IO_STANDARD_LVCMOS18>;
297 drive-strength = <12>;
301 pinctrl_gem3_default: gem3-default {
309 slew-rate = <SLEW_RATE_SLOW>;
310 power-source = <IO_STANDARD_LVCMOS18>;
311 drive-strength = <12>;
314 conf-rx {
317 bias-high-impedance;
318 low-power-disable;
321 conf-tx {
324 bias-disable;
325 low-power-enable;
328 mux-mdio {
333 conf-mdio {
335 slew-rate = <SLEW_RATE_SLOW>;
336 power-source = <IO_STANDARD_LVCMOS18>;
337 bias-disable;
341 pinctrl_sdhci1_default: sdhci1-default {
349 slew-rate = <SLEW_RATE_SLOW>;
350 power-source = <IO_STANDARD_LVCMOS18>;
351 bias-disable;
352 drive-strength = <12>;
355 mux-cd {
360 conf-cd {
362 bias-high-impedance;
363 bias-pull-up;
364 slew-rate = <SLEW_RATE_SLOW>;
365 power-source = <IO_STANDARD_LVCMOS18>;
369 pinctrl_uart0_default: uart0-default {
377 slew-rate = <SLEW_RATE_SLOW>;
378 power-source = <IO_STANDARD_LVCMOS18>;
379 drive-strength = <12>;
382 conf-rx {
384 bias-high-impedance;
387 conf-tx {
389 bias-disable;
393 pinctrl_uart1_default: uart1-default {
401 slew-rate = <SLEW_RATE_SLOW>;
402 power-source = <IO_STANDARD_LVCMOS18>;
403 drive-strength = <12>;
406 conf-rx {
408 bias-high-impedance;
411 conf-tx {
413 bias-disable;
417 pinctrl_usb0_default: usb0-default {
425 power-source = <IO_STANDARD_LVCMOS18>;
428 conf-rx {
430 bias-high-impedance;
431 drive-strength = <12>;
432 slew-rate = <SLEW_RATE_FAST>;
435 conf-tx {
438 bias-disable;
439 drive-strength = <4>;
440 slew-rate = <SLEW_RATE_SLOW>;
449 clock-names = "ref1", "ref2", "ref3";
455 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
456 #address-cells = <1>;
457 #size-cells = <1>;
459 spi-tx-bus-width = <4>;
460 spi-rx-bus-width = <4>;
461 spi-max-frequency = <108000000>; /* Based on DC1 spec */
472 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
473 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
474 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
475 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
476 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
477 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
478 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
479 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
480 phy-names = "sata-phy";
487 no-1-8-v;
488 pinctrl-names = "default";
489 pinctrl-0 = <&pinctrl_sdhci1_default>;
490 xlnx,mio-bank = <1>;
491 disable-wp;
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_uart0_default>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_uart1_default>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&pinctrl_usb0_default>;
511 phy-names = "usb3-phy";
519 maximum-speed = "super-speed";
544 phy-names = "dp-phy0", "dp-phy1";