Lines Matching +full:p1 +full:- +full:retry +full:- +full:params
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <125000000>;
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <26000000>;
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <27000000>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_can1_default>;
109 phy-handle = <&phy0>;
110 phy-mode = "rgmii-id";
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_gem3_default>;
114 #address-cells = <1>;
115 #size-cells = <0>;
116 phy0: ethernet-phy@c {
117 #phy-cells = <1>;
118 compatible = "ethernet-phy-id2000.a231";
120 ti,rx-internal-delay = <0x8>;
121 ti,tx-internal-delay = <0xa>;
122 ti,fifo-depth = <0x1>;
123 ti,dp83867-rxctrl-strap-quirk;
124 reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
139 clock-frequency = <400000>;
140 pinctrl-names = "default", "gpio";
141 pinctrl-0 = <&pinctrl_i2c1_default>;
142 pinctrl-1 = <&pinctrl_i2c1_gpio>;
143 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
144 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
146 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
147 i2c-mux@74 { /* u34 */
149 #address-cells = <1>;
150 #size-cells = <0>;
153 #address-cells = <1>;
154 #size-cells = <0>;
159 * 0 - 256B address 0x54
160 * 256B - 512B address 0x55
161 * 512B - 768B address 0x56
162 * 768B - 1024B address 0x57
167 #address-cells = <1>;
168 #size-cells = <1>;
173 #address-cells = <1>;
174 #size-cells = <0>;
176 /* 8T49N287 - u182 */
180 #address-cells = <1>;
181 #size-cells = <0>;
183 irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
187 irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
194 #address-cells = <1>;
195 #size-cells = <0>;
200 gpio-controller;
201 #gpio-cells = <2>;
205 * 0 - IRPS5401_ALERT_B
206 * 1 - HDMI_8T49N241_INT_ALM
207 * 2 - MAX6643_OT_B
208 * 3 - MAX6643_FANFAIL_B
209 * 5 - IIC_MUX_RESET_B
210 * 6 - GEM3_EXP_RESET_B
211 * 7 - FMC_LPC_PRSNT_M2C_B
212 * 4, 10 - 17 - not connected
218 #address-cells = <1>;
219 #size-cells = <0>;
224 #address-cells = <1>;
225 #size-cells = <0>;
236 pinctrl_can1_default: can1-default {
244 slew-rate = <SLEW_RATE_SLOW>;
245 power-source = <IO_STANDARD_LVCMOS18>;
246 drive-strength = <12>;
249 conf-rx {
251 bias-high-impedance;
254 conf-tx {
256 bias-disable;
260 pinctrl_i2c1_default: i2c1-default {
268 bias-pull-up;
269 slew-rate = <SLEW_RATE_SLOW>;
270 power-source = <IO_STANDARD_LVCMOS18>;
271 drive-strength = <12>;
275 pinctrl_i2c1_gpio: i2c1-gpio-grp {
283 slew-rate = <SLEW_RATE_SLOW>;
284 power-source = <IO_STANDARD_LVCMOS18>;
285 drive-strength = <12>;
289 pinctrl_gem3_default: gem3-default {
297 slew-rate = <SLEW_RATE_SLOW>;
298 power-source = <IO_STANDARD_LVCMOS18>;
299 drive-strength = <12>;
302 conf-rx {
305 bias-high-impedance;
306 low-power-disable;
309 conf-tx {
312 bias-disable;
313 low-power-enable;
316 mux-mdio {
321 conf-mdio {
323 slew-rate = <SLEW_RATE_SLOW>;
324 power-source = <IO_STANDARD_LVCMOS18>;
325 bias-disable;
329 pinctrl_sdhci1_default: sdhci1-default {
337 slew-rate = <SLEW_RATE_SLOW>;
338 power-source = <IO_STANDARD_LVCMOS18>;
339 bias-disable;
340 drive-strength = <12>;
343 mux-cd {
348 conf-cd {
350 bias-high-impedance;
351 bias-pull-up;
352 slew-rate = <SLEW_RATE_SLOW>;
353 power-source = <IO_STANDARD_LVCMOS18>;
357 pinctrl_uart0_default: uart0-default {
365 slew-rate = <SLEW_RATE_SLOW>;
366 power-source = <IO_STANDARD_LVCMOS18>;
367 drive-strength = <12>;
370 conf-rx {
372 bias-high-impedance;
375 conf-tx {
377 bias-disable;
381 pinctrl_uart1_default: uart1-default {
389 slew-rate = <SLEW_RATE_SLOW>;
390 power-source = <IO_STANDARD_LVCMOS18>;
391 drive-strength = <12>;
394 conf-rx {
396 bias-high-impedance;
399 conf-tx {
401 bias-disable;
405 pinctrl_usb0_default: usb0-default {
413 power-source = <IO_STANDARD_LVCMOS18>;
416 conf-rx {
418 bias-high-impedance;
419 drive-strength = <12>;
420 slew-rate = <SLEW_RATE_FAST>;
423 conf-tx {
426 bias-disable;
427 drive-strength = <4>;
428 slew-rate = <SLEW_RATE_SLOW>;
437 clock-names = "ref1", "ref2", "ref3";
443 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
444 #address-cells = <1>;
445 #size-cells = <1>;
447 spi-tx-bus-width = <4>;
448 spi-rx-bus-width = <4>;
449 spi-max-frequency = <108000000>; /* Based on DC1 spec */
460 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
461 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
462 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
463 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
464 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
465 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
466 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
467 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
468 phy-names = "sata-phy";
475 no-1-8-v;
476 pinctrl-names = "default";
477 pinctrl-0 = <&pinctrl_sdhci1_default>;
478 xlnx,mio-bank = <1>;
479 disable-wp;
484 pinctrl-names = "default";
485 pinctrl-0 = <&pinctrl_uart0_default>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&pinctrl_uart1_default>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&pinctrl_usb0_default>;
499 phy-names = "usb3-phy";
507 maximum-speed = "super-speed";
532 phy-names = "dp-phy0", "dp-phy1";