Lines Matching +full:zynqmp +full:- +full:psgtr +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevA
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
21 model = "ZynqMP ZCU102 RevA";
22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
40 stdout-path = "serial0:115200n8";
48 gpio-keys {
49 compatible = "gpio-keys";
51 switch-19 {
55 wakeup-source;
61 compatible = "gpio-leds";
62 heartbeat-led {
65 linux,default-trigger = "heartbeat";
69 ina226-u76 {
70 compatible = "iio-hwmon";
71 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
73 ina226-u77 {
74 compatible = "iio-hwmon";
75 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
77 ina226-u78 {
78 compatible = "iio-hwmon";
79 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
81 ina226-u87 {
82 compatible = "iio-hwmon";
83 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
85 ina226-u85 {
86 compatible = "iio-hwmon";
87 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
89 ina226-u86 {
90 compatible = "iio-hwmon";
91 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
93 ina226-u93 {
94 compatible = "iio-hwmon";
95 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
97 ina226-u88 {
98 compatible = "iio-hwmon";
99 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
101 ina226-u15 {
102 compatible = "iio-hwmon";
103 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
105 ina226-u92 {
106 compatible = "iio-hwmon";
107 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
109 ina226-u79 {
110 compatible = "iio-hwmon";
111 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
113 ina226-u81 {
114 compatible = "iio-hwmon";
115 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
117 ina226-u80 {
118 compatible = "iio-hwmon";
119 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
121 ina226-u84 {
122 compatible = "iio-hwmon";
123 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
125 ina226-u16 {
126 compatible = "iio-hwmon";
127 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
129 ina226-u65 {
130 compatible = "iio-hwmon";
131 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
133 ina226-u74 {
134 compatible = "iio-hwmon";
135 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
137 ina226-u75 {
138 compatible = "iio-hwmon";
139 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
144 compatible = "fixed-clock";
145 #clock-cells = <0>;
146 clock-frequency = <48000000>;
150 compatible = "fixed-clock";
151 #clock-cells = <0>;
152 clock-frequency = <114285000>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_can1_default>;
200 phy-handle = <&phy0>;
201 phy-mode = "rgmii-id";
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_gem3_default>;
205 #address-cells = <1>;
206 #size-cells = <0>;
207 phy0: ethernet-phy@21 {
208 #phy-cells = <1>;
209 compatible = "ethernet-phy-id2000.a231";
211 ti,rx-internal-delay = <0x8>;
212 ti,tx-internal-delay = <0xa>;
213 ti,fifo-depth = <0x1>;
214 ti,dp83867-rxctrl-strap-quirk;
215 reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_gpio_default>;
232 clock-frequency = <400000>;
233 pinctrl-names = "default", "gpio";
234 pinctrl-0 = <&pinctrl_i2c0_default>;
235 pinctrl-1 = <&pinctrl_i2c0_gpio>;
236 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
237 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
242 gpio-controller; /* IRQ not connected */
243 #gpio-cells = <2>;
244 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
247 gtr-sel0-hog {
248 gpio-hog;
250 output-low; /* PCIE = 0, DP = 1 */
251 line-name = "sel0";
253 gtr-sel1-hog {
254 gpio-hog;
256 output-high; /* PCIE = 0, DP = 1 */
257 line-name = "sel1";
259 gtr-sel2-hog {
260 gpio-hog;
262 output-high; /* PCIE = 0, USB0 = 1 */
263 line-name = "sel2";
265 gtr-sel3-hog {
266 gpio-hog;
268 output-high; /* PCIE = 0, SATA = 1 */
269 line-name = "sel3";
276 gpio-controller; /* IRQ not connected */
277 #gpio-cells = <2>;
278 …gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_…
284 i2c-mux@75 { /* u60 */
286 #address-cells = <1>;
287 #size-cells = <0>;
290 #address-cells = <1>;
291 #size-cells = <0>;
296 #io-channel-cells = <1>;
297 label = "ina226-u76";
299 shunt-resistor = <5000>;
303 #io-channel-cells = <1>;
304 label = "ina226-u77";
306 shunt-resistor = <5000>;
310 #io-channel-cells = <1>;
311 label = "ina226-u78";
313 shunt-resistor = <5000>;
317 #io-channel-cells = <1>;
318 label = "ina226-u87";
320 shunt-resistor = <5000>;
324 #io-channel-cells = <1>;
325 label = "ina226-u85";
327 shunt-resistor = <5000>;
331 #io-channel-cells = <1>;
332 label = "ina226-u86";
334 shunt-resistor = <5000>;
338 #io-channel-cells = <1>;
339 label = "ina226-u93";
341 shunt-resistor = <5000>;
345 #io-channel-cells = <1>;
346 label = "ina226-u88";
348 shunt-resistor = <5000>;
352 #io-channel-cells = <1>;
353 label = "ina226-u15";
355 shunt-resistor = <5000>;
359 #io-channel-cells = <1>;
360 label = "ina226-u92";
362 shunt-resistor = <5000>;
366 #address-cells = <1>;
367 #size-cells = <0>;
372 #io-channel-cells = <1>;
373 label = "ina226-u79";
375 shunt-resistor = <2000>;
379 #io-channel-cells = <1>;
380 label = "ina226-u81";
382 shunt-resistor = <5000>;
386 #io-channel-cells = <1>;
387 label = "ina226-u80";
389 shunt-resistor = <5000>;
393 #io-channel-cells = <1>;
394 label = "ina226-u84";
396 shunt-resistor = <5000>;
400 #io-channel-cells = <1>;
401 label = "ina226-u16";
403 shunt-resistor = <5000>;
407 #io-channel-cells = <1>;
408 label = "ina226-u65";
410 shunt-resistor = <5000>;
414 #io-channel-cells = <1>;
415 label = "ina226-u74";
417 shunt-resistor = <5000>;
421 #io-channel-cells = <1>;
422 label = "ina226-u75";
424 shunt-resistor = <5000>;
428 #address-cells = <1>;
429 #size-cells = <0>;
431 /* MAXIM_PMBUS - 00 */
496 clock-frequency = <400000>;
497 pinctrl-names = "default", "gpio";
498 pinctrl-0 = <&pinctrl_i2c1_default>;
499 pinctrl-1 = <&pinctrl_i2c1_gpio>;
500 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
501 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
503 /* PL i2c via PCA9306 - u45 */
504 i2c-mux@74 { /* u34 */
506 #address-cells = <1>;
507 #size-cells = <0>;
510 #address-cells = <1>;
511 #size-cells = <0>;
516 * 0 - 256B address 0x54
517 * 256B - 512B address 0x55
518 * 512B - 768B address 0x56
519 * 768B - 1024B address 0x57
527 #address-cells = <1>;
528 #size-cells = <0>;
530 si5341: clock-generator@36 { /* SI5341 - u69 */
533 #clock-cells = <2>;
534 #address-cells = <1>;
535 #size-cells = <0>;
537 clock-names = "xtal";
538 clock-output-names = "si5341";
541 /* refclk0 for PS-GT, used for DP */
543 always-on;
546 /* refclk2 for PS-GT, used for USB3 */
548 always-on;
551 /* refclk3 for PS-GT, used for SATA */
553 always-on;
556 /* refclk4 for PS-GT, used for PCIE slot */
558 always-on;
561 /* refclk5 for PS-GT, used for PCIE */
563 always-on;
568 always-on;
573 always-on;
578 always-on;
583 #address-cells = <1>;
584 #size-cells = <0>;
586 si570_1: clock-generator@5d { /* USER SI570 - u42 */
587 #clock-cells = <0>;
590 temperature-stability = <50>;
591 factory-fout = <300000000>;
592 clock-frequency = <300000000>;
593 clock-output-names = "si570_user";
597 #address-cells = <1>;
598 #size-cells = <0>;
600 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
601 #clock-cells = <0>;
604 temperature-stability = <50>; /* copy from zc702 */
605 factory-fout = <156250000>;
606 clock-frequency = <156250000>;
607 clock-output-names = "si570_mgt";
611 #address-cells = <1>;
612 #size-cells = <0>;
614 /* SI5328 - u20 */
616 /* 5 - 7 unconnected */
619 i2c-mux@75 {
621 #address-cells = <1>;
622 #size-cells = <0>;
626 #address-cells = <1>;
627 #size-cells = <0>;
632 #address-cells = <1>;
633 #size-cells = <0>;
638 #address-cells = <1>;
639 #size-cells = <0>;
644 #address-cells = <1>;
645 #size-cells = <0>;
650 #address-cells = <1>;
651 #size-cells = <0>;
656 #address-cells = <1>;
657 #size-cells = <0>;
662 #address-cells = <1>;
663 #size-cells = <0>;
668 #address-cells = <1>;
669 #size-cells = <0>;
678 pinctrl_i2c0_default: i2c0-default {
686 bias-pull-up;
687 slew-rate = <SLEW_RATE_SLOW>;
688 power-source = <IO_STANDARD_LVCMOS18>;
692 pinctrl_i2c0_gpio: i2c0-gpio-grp {
700 slew-rate = <SLEW_RATE_SLOW>;
701 power-source = <IO_STANDARD_LVCMOS18>;
705 pinctrl_i2c1_default: i2c1-default {
713 bias-pull-up;
714 slew-rate = <SLEW_RATE_SLOW>;
715 power-source = <IO_STANDARD_LVCMOS18>;
719 pinctrl_i2c1_gpio: i2c1-gpio-grp {
727 slew-rate = <SLEW_RATE_SLOW>;
728 power-source = <IO_STANDARD_LVCMOS18>;
732 pinctrl_uart0_default: uart0-default {
740 slew-rate = <SLEW_RATE_SLOW>;
741 power-source = <IO_STANDARD_LVCMOS18>;
744 conf-rx {
746 bias-high-impedance;
749 conf-tx {
751 bias-disable;
755 pinctrl_uart1_default: uart1-default {
763 slew-rate = <SLEW_RATE_SLOW>;
764 power-source = <IO_STANDARD_LVCMOS18>;
767 conf-rx {
769 bias-high-impedance;
772 conf-tx {
774 bias-disable;
778 pinctrl_usb0_default: usb0-default {
786 power-source = <IO_STANDARD_LVCMOS18>;
789 conf-rx {
791 bias-high-impedance;
792 drive-strength = <12>;
793 slew-rate = <SLEW_RATE_FAST>;
796 conf-tx {
799 bias-disable;
800 drive-strength = <4>;
801 slew-rate = <SLEW_RATE_SLOW>;
805 pinctrl_gem3_default: gem3-default {
813 slew-rate = <SLEW_RATE_SLOW>;
814 power-source = <IO_STANDARD_LVCMOS18>;
817 conf-rx {
820 bias-high-impedance;
821 low-power-disable;
824 conf-tx {
827 bias-disable;
828 low-power-enable;
831 mux-mdio {
836 conf-mdio {
838 slew-rate = <SLEW_RATE_SLOW>;
839 power-source = <IO_STANDARD_LVCMOS18>;
840 bias-disable;
844 pinctrl_can1_default: can1-default {
852 slew-rate = <SLEW_RATE_SLOW>;
853 power-source = <IO_STANDARD_LVCMOS18>;
856 conf-rx {
858 bias-high-impedance;
861 conf-tx {
863 bias-disable;
867 pinctrl_sdhci1_default: sdhci1-default {
875 slew-rate = <SLEW_RATE_SLOW>;
876 power-source = <IO_STANDARD_LVCMOS18>;
877 bias-disable;
880 mux-cd {
885 conf-cd {
887 bias-high-impedance;
888 bias-pull-up;
889 slew-rate = <SLEW_RATE_SLOW>;
890 power-source = <IO_STANDARD_LVCMOS18>;
893 mux-wp {
898 conf-wp {
900 bias-high-impedance;
901 bias-pull-up;
902 slew-rate = <SLEW_RATE_SLOW>;
903 power-source = <IO_STANDARD_LVCMOS18>;
907 pinctrl_gpio_default: gpio-default {
908 mux-sw {
913 conf-sw {
915 slew-rate = <SLEW_RATE_SLOW>;
916 power-source = <IO_STANDARD_LVCMOS18>;
919 mux-msp {
924 conf-msp {
926 slew-rate = <SLEW_RATE_SLOW>;
927 power-source = <IO_STANDARD_LVCMOS18>;
930 conf-pull-up {
932 bias-pull-up;
935 conf-pull-none {
937 bias-disable;
944 phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
947 &psgtr {
951 clock-names = "ref0", "ref1", "ref2", "ref3";
957 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
958 #address-cells = <1>;
959 #size-cells = <1>;
961 spi-tx-bus-width = <4>;
962 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
963 spi-max-frequency = <108000000>; /* Based on DC1 spec */
974 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
975 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
976 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
977 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
978 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
979 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
980 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
981 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
982 phy-names = "sata-phy";
983 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
993 no-1-8-v;
994 pinctrl-names = "default";
995 pinctrl-0 = <&pinctrl_sdhci1_default>;
996 xlnx,mio-bank = <1>;
1001 pinctrl-names = "default";
1002 pinctrl-0 = <&pinctrl_uart0_default>;
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&pinctrl_uart1_default>;
1014 pinctrl-names = "default";
1015 pinctrl-0 = <&pinctrl_usb0_default>;
1016 phy-names = "usb3-phy";
1017 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
1024 maximum-speed = "super-speed";
1045 phy-names = "dp-phy0";
1046 phys = <&psgtr 1 PHY_TYPE_DP 0 3>;