Lines Matching +full:bias +full:- +full:disable
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
76 phy-handle = <&phy0>;
77 phy-mode = "rgmii-id";
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_gem1_default>;
81 #address-cells = <1>;
82 #size-cells = <0>;
83 phy0: ethernet-phy@0 {
95 pinctrl-names = "default", "gpio";
96 pinctrl-0 = <&pinctrl_i2c0_default>;
97 pinctrl-1 = <&pinctrl_i2c0_gpio>;
98 scl-gpios = <&gpio 74 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
99 sda-gpios = <&gpio 75 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
104 pinctrl-names = "default", "gpio";
105 pinctrl-0 = <&pinctrl_i2c1_default>;
106 pinctrl-1 = <&pinctrl_i2c1_gpio>;
107 scl-gpios = <&gpio 76 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
108 sda-gpios = <&gpio 77 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
114 pinctrl_i2c0_default: i2c0-default {
122 bias-pull-up;
123 slew-rate = <SLEW_RATE_SLOW>;
124 power-source = <IO_STANDARD_LVCMOS18>;
128 pinctrl_i2c0_gpio: i2c0-gpio-grp {
136 slew-rate = <SLEW_RATE_SLOW>;
137 power-source = <IO_STANDARD_LVCMOS18>;
141 pinctrl_i2c1_default: i2c1-default {
149 bias-pull-up;
150 slew-rate = <SLEW_RATE_SLOW>;
151 power-source = <IO_STANDARD_LVCMOS18>;
155 pinctrl_i2c1_gpio: i2c1-gpio-grp {
163 slew-rate = <SLEW_RATE_SLOW>;
164 power-source = <IO_STANDARD_LVCMOS18>;
168 pinctrl_uart0_default: uart0-default {
176 slew-rate = <SLEW_RATE_SLOW>;
177 power-source = <IO_STANDARD_LVCMOS18>;
180 conf-rx {
182 bias-high-impedance;
185 conf-tx {
187 bias-disable;
191 pinctrl_uart1_default: uart1-default {
199 slew-rate = <SLEW_RATE_SLOW>;
200 power-source = <IO_STANDARD_LVCMOS18>;
203 conf-rx {
205 bias-high-impedance;
208 conf-tx {
210 bias-disable;
214 pinctrl_gem1_default: gem1-default {
222 slew-rate = <SLEW_RATE_SLOW>;
223 power-source = <IO_STANDARD_LVCMOS18>;
226 conf-rx {
229 bias-high-impedance;
230 low-power-disable;
233 conf-tx {
236 bias-disable;
237 low-power-enable;
240 mux-mdio {
245 conf-mdio {
247 slew-rate = <SLEW_RATE_SLOW>;
248 power-source = <IO_STANDARD_LVCMOS18>;
249 bias-disable;
253 pinctrl_sdhci0_default: sdhci0-default {
261 slew-rate = <SLEW_RATE_SLOW>;
262 power-source = <IO_STANDARD_LVCMOS18>;
263 bias-disable;
266 mux-cd {
271 conf-cd {
273 bias-high-impedance;
274 bias-pull-up;
275 slew-rate = <SLEW_RATE_SLOW>;
276 power-source = <IO_STANDARD_LVCMOS18>;
279 mux-wp {
284 conf-wp {
286 bias-high-impedance;
287 bias-pull-up;
288 slew-rate = <SLEW_RATE_SLOW>;
289 power-source = <IO_STANDARD_LVCMOS18>;
293 pinctrl_watchdog0_default: watchdog0-default {
294 mux-clk {
299 conf-clk {
301 bias-pull-up;
304 mux-rst {
309 conf-rst {
311 bias-disable;
312 slew-rate = <SLEW_RATE_SLOW>;
316 pinctrl_ttc0_default: ttc0-default {
317 mux-clk {
322 conf-clk {
324 bias-pull-up;
327 mux-wav {
332 conf-wav {
334 bias-disable;
335 slew-rate = <SLEW_RATE_SLOW>;
339 pinctrl_ttc1_default: ttc1-default {
340 mux-clk {
345 conf-clk {
347 bias-pull-up;
350 mux-wav {
355 conf-wav {
357 bias-disable;
358 slew-rate = <SLEW_RATE_SLOW>;
362 pinctrl_ttc2_default: ttc2-default {
363 mux-clk {
368 conf-clk {
370 bias-pull-up;
373 mux-wav {
378 conf-wav {
380 bias-disable;
381 slew-rate = <SLEW_RATE_SLOW>;
385 pinctrl_ttc3_default: ttc3-default {
386 mux-clk {
391 conf-clk {
393 bias-pull-up;
396 mux-wav {
401 conf-wav {
403 bias-disable;
404 slew-rate = <SLEW_RATE_SLOW>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_sdhci0_default>;
413 no-1-8-v;
414 xlnx,mio-bank = <0>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&pinctrl_ttc0_default>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&pinctrl_ttc1_default>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_ttc2_default>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&pinctrl_ttc3_default>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_uart0_default>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_uart1_default>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&pinctrl_watchdog0_default>;