Lines Matching +full:ref2 +full:-
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
5 * (C) Copyright 2016 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/phy/phy.h>
17 model = "ZynqMP zc1751-xm017-dc3 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <26000000>;
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <125000000>;
89 phy-handle = <&phy0>;
90 phy-mode = "rgmii-id";
92 #address-cells = <1>;
93 #size-cells = <0>;
94 phy0: ethernet-phy@0 { /* VSC8211 */
107 clock-frequency = <400000>;
112 gpio-controller;
113 #gpio-cells = <2>;
126 clock-frequency = <400000>;
129 /* MT29F64G08AECDBJ4-6 */
132 arasan,has-mdma;
133 num-cs = <2>;
140 clock-names = "ref2", "ref3";
150 ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
151 ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
152 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
153 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
154 ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
155 ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
156 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
157 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
158 phy-names = "sata-phy";
178 phy-names = "usb3-phy";
186 maximum-speed = "super-speed";
192 phy-names = "usb3-phy";
200 maximum-speed = "super-speed";