Lines Matching +full:high +full:- +full:power
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
21 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
36 stdout-path = "serial0:115200n8";
44 clock_si5338_0: clk27 { /* u55 SI5338-GM */
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <27000000>;
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <26000000>;
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <150000000>;
97 phy-handle = <&phy0>;
98 phy-mode = "rgmii-id";
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_gem3_default>;
102 #address-cells = <1>;
103 #size-cells = <0>;
104 phy0: ethernet-phy@0 {
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_gpio_default>;
122 clock-frequency = <400000>;
123 pinctrl-names = "default", "gpio";
124 pinctrl-0 = <&pinctrl_i2c1_default>;
125 pinctrl-1 = <&pinctrl_i2c1_gpio>;
126 scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
127 sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
137 pinctrl_i2c1_default: i2c1-default {
145 bias-pull-up;
146 slew-rate = <SLEW_RATE_SLOW>;
147 power-source = <IO_STANDARD_LVCMOS18>;
151 pinctrl_i2c1_gpio: i2c1-gpio-grp {
159 slew-rate = <SLEW_RATE_SLOW>;
160 power-source = <IO_STANDARD_LVCMOS18>;
164 pinctrl_uart0_default: uart0-default {
172 slew-rate = <SLEW_RATE_SLOW>;
173 power-source = <IO_STANDARD_LVCMOS18>;
176 conf-rx {
178 bias-high-impedance;
181 conf-tx {
183 bias-disable;
187 pinctrl_usb0_default: usb0-default {
195 power-source = <IO_STANDARD_LVCMOS18>;
198 conf-rx {
200 bias-high-impedance;
201 drive-strength = <12>;
202 slew-rate = <SLEW_RATE_FAST>;
205 conf-tx {
208 bias-disable;
209 drive-strength = <4>;
210 slew-rate = <SLEW_RATE_SLOW>;
214 pinctrl_gem3_default: gem3-default {
222 slew-rate = <SLEW_RATE_SLOW>;
223 power-source = <IO_STANDARD_LVCMOS18>;
226 conf-rx {
229 bias-high-impedance;
230 low-power-disable;
233 conf-tx {
236 bias-disable;
237 low-power-enable;
240 mux-mdio {
245 conf-mdio {
247 slew-rate = <SLEW_RATE_SLOW>;
248 power-source = <IO_STANDARD_LVCMOS18>;
249 bias-disable;
253 pinctrl_sdhci0_default: sdhci0-default {
261 slew-rate = <SLEW_RATE_SLOW>;
262 power-source = <IO_STANDARD_LVCMOS18>;
263 bias-disable;
266 mux-cd {
271 conf-cd {
273 bias-high-impedance;
274 bias-pull-up;
275 slew-rate = <SLEW_RATE_SLOW>;
276 power-source = <IO_STANDARD_LVCMOS18>;
279 mux-wp {
284 conf-wp {
286 bias-high-impedance;
287 bias-pull-up;
288 slew-rate = <SLEW_RATE_SLOW>;
289 power-source = <IO_STANDARD_LVCMOS18>;
293 pinctrl_sdhci1_default: sdhci1-default {
301 slew-rate = <SLEW_RATE_SLOW>;
302 power-source = <IO_STANDARD_LVCMOS18>;
303 bias-disable;
306 mux-cd {
311 conf-cd {
313 bias-high-impedance;
314 bias-pull-up;
315 slew-rate = <SLEW_RATE_SLOW>;
316 power-source = <IO_STANDARD_LVCMOS18>;
319 mux-wp {
324 conf-wp {
326 bias-high-impedance;
327 bias-pull-up;
328 slew-rate = <SLEW_RATE_SLOW>;
329 power-source = <IO_STANDARD_LVCMOS18>;
333 pinctrl_gpio_default: gpio-default {
341 bias-disable;
342 slew-rate = <SLEW_RATE_SLOW>;
343 power-source = <IO_STANDARD_LVCMOS18>;
352 clock-names = "ref1", "ref2", "ref3";
358 compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
359 #address-cells = <1>;
360 #size-cells = <1>;
362 spi-tx-bus-width = <4>;
363 spi-rx-bus-width = <4>;
364 spi-max-frequency = <108000000>; /* Based on DC1 spec */
375 ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
376 ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
377 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
378 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
379 ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
380 ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
381 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
382 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
383 phy-names = "sata-phy";
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_sdhci0_default>;
392 bus-width = <8>;
393 xlnx,mio-bank = <0>;
402 no-1-8-v;
403 pinctrl-names = "default";
404 pinctrl-0 = <&pinctrl_sdhci1_default>;
405 xlnx,mio-bank = <1>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_uart0_default>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&pinctrl_usb0_default>;
419 phy-names = "usb3-phy";
427 maximum-speed = "super-speed";
436 phy-names = "dp-phy0", "dp-phy1";