Lines Matching +full:p1 +full:- +full:comwake +full:- +full:params
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
27 stdout-path = "serial0:115200n8";
43 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
44 #address-cells = <1>;
45 #size-cells = <1>;
47 spi-tx-bus-width = <4>;
48 spi-rx-bus-width = <4>;
49 spi-max-frequency = <108000000>; /* Based on DC1 spec */
56 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
57 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
58 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
59 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
60 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
61 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
62 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
63 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;