Lines Matching +full:fw +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
6 * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
21 model = "ZynqMP SM-K26 Rev2/1/B/A";
22 compatible = "xlnx,zynqmp-sm-k26-rev2",
23 "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
24 "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
47 stdout-path = "serial1:115200n8";
55 reserved-memory {
56 #address-cells = <2>;
57 #size-cells = <2>;
62 no-map;
66 gpio-keys {
67 compatible = "gpio-keys";
69 key-fwuen {
71 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
73 wakeup-source;
79 compatible = "gpio-leds";
80 ds35-led {
82 gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
83 linux,default-trigger = "heartbeat";
86 ds36-led {
88 gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
89 default-state = "on";
94 compatible = "iio-hwmon";
95 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
107 pwm-fan {
108 compatible = "pwm-fan";
120 #pwm-cells = <3>;
129 pinctrl_sdhci0_default: sdhci0-default {
132 slew-rate = <SLEW_RATE_SLOW>;
133 power-source = <IO_STANDARD_LVCMOS18>;
134 bias-disable;
144 &qspi { /* MIO 0-5 - U143 */
147 compatible = "jedec,spi-nor"; /* 64MB */
149 spi-tx-bus-width = <4>;
150 spi-rx-bus-width = <4>;
151 spi-max-frequency = <40000000>; /* 40MHz */
154 compatible = "fixed-partitions";
155 #address-cells = <1>;
156 #size-cells = <1>;
161 read-only;
167 read-only;
183 label = "Image A (FSBL, PMU, ATF, U-Boot)";
189 read-only;
193 label = "Image B (FSBL, PMU, ATF, U-Boot)";
199 read-only;
209 read-only;
215 read-only;
219 label = "U-Boot storage variables";
223 label = "U-Boot storage variables backup";
229 read-only;
244 &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_sdhci0_default>;
248 non-removable;
249 disable-wp;
250 bus-width = <8>;
251 xlnx,mio-bank = <0>;
252 assigned-clock-rates = <187498123>;
255 &spi1 { /* MIO6, 9-11 */
258 num-cs = <1>;
259 tpm@0 { /* slm9670 - U144 */
260 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
262 spi-max-frequency = <18500000>;
268 bootph-all;
269 clock-frequency = <400000>;
270 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
271 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
273 eeprom: eeprom@50 { /* u46 - also at address 0x58 */
274 bootph-all;
280 eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
281 bootph-all;
286 /* da9062@30 - u170 - also at address 0x31 */
287 /* da9131@33 - u167 */
293 regulator-name = "da9131_buck1";
294 regulator-boot-on;
295 regulator-always-on;
298 regulator-name = "da9131_buck2";
299 regulator-boot-on;
300 regulator-always-on;
305 /* da9130@32 - u166 */
311 regulator-name = "da9130_buck1";
312 regulator-boot-on;
313 regulator-always-on;
318 /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
320 * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
323 * With the FW fix, stdp4320 should respond to address 0x73 only.
325 /* slg7x644092@68 - u169 */
331 gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
332 "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
333 "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
334 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
335 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
336 "I2C1_SDA", "", "", "", "", /* 25 - 29 */
337 "", "", "", "", "", /* 30 - 34 */
338 "", "", "", "", "", /* 35 - 39 */
339 "", "", "", "", "", /* 40 - 44 */
340 "", "", "", "", "", /* 45 - 49 */
341 "", "", "", "", "", /* 50 - 54 */
342 "", "", "", "", "", /* 55 - 59 */
343 "", "", "", "", "", /* 60 - 64 */
344 "", "", "", "", "", /* 65 - 69 */
345 "", "", "", "", "", /* 70 - 74 */
346 "", "", "", /* 75 - 77, MIO end and EMIO start */
347 "", "", /* 78 - 79 */
348 "", "", "", "", "", /* 80 - 84 */
349 "", "", "", "", "", /* 85 - 89 */
350 "", "", "", "", "", /* 90 - 94 */
351 "", "", "", "", "", /* 95 - 99 */
352 "", "", "", "", "", /* 100 - 104 */
353 "", "", "", "", "", /* 105 - 109 */
354 "", "", "", "", "", /* 110 - 114 */
355 "", "", "", "", "", /* 115 - 119 */
356 "", "", "", "", "", /* 120 - 124 */
357 "", "", "", "", "", /* 125 - 129 */
358 "", "", "", "", "", /* 130 - 134 */
359 "", "", "", "", "", /* 135 - 139 */
360 "", "", "", "", "", /* 140 - 144 */
361 "", "", "", "", "", /* 145 - 149 */
362 "", "", "", "", "", /* 150 - 154 */
363 "", "", "", "", "", /* 155 - 159 */
364 "", "", "", "", "", /* 160 - 164 */
365 "", "", "", "", "", /* 165 - 169 */
366 "", "", "", ""; /* 170 - 173 */
467 opp-hz = /bits/ 64 <1333333333>;
470 opp-hz = /bits/ 64 <666666666>;
473 opp-hz = /bits/ 64 <444444444>;
476 opp-hz = /bits/ 64 <333333333>;