Lines Matching +full:conf +full:- +full:tx
1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 compatible = "xlnx,zynqmp-sk-kv260-rev2",
21 "xlnx,zynqmp-sk-kv260-rev1",
22 "xlnx,zynqmp-sk-kv260-revB",
23 "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
26 ina260-u14 {
27 compatible = "iio-hwmon";
28 io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
31 si5332_0: si5332-0 { /* u17 */
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <125000000>;
37 si5332_1: si5332-1 { /* u17 */
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <25000000>;
43 si5332_2: si5332-2 { /* u17 */
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <48000000>;
49 si5332_3: si5332-3 { /* u17 */
50 compatible = "fixed-clock";
51 #clock-cells = <0>;
52 clock-frequency = <24000000>;
55 si5332_4: si5332-4 { /* u17 */
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <26000000>;
61 si5332_5: si5332-5 { /* u17 */
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <27000000>;
68 compatible = "dp-connector";
70 type = "full-size";
74 remote-endpoint = <&dpsub_dp_out>;
80 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
81 #address-cells = <1>;
82 #size-cells = <0>;
83 pinctrl-names = "default", "gpio";
84 pinctrl-0 = <&pinctrl_i2c1_default>;
85 pinctrl-1 = <&pinctrl_i2c1_gpio>;
86 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
87 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
91 #io-channel-cells = <1>;
92 label = "ina260-u14";
95 /* u43 - 0x2d - USB hub */
96 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
104 clock-names = "ref0", "ref1", "ref2";
109 phy-names = "dp-phy0", "dp-phy1";
111 assigned-clock-rates = <27000000>, <25000000>, <300000000>;
116 remote-endpoint = <&dpcon_in>;
124 assigned-clock-rates = <600000000>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_usb0_default>;
131 phy-names = "usb3-phy";
133 assigned-clock-rates = <250000000>, <20000000>;
140 maximum-speed = "super-speed";
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_sdhci1_default>;
152 no-1-8-v;
153 disable-wp;
154 xlnx,mio-bank = <1>;
155 clk-phase-sd-hs = <126>, <60>;
156 clk-phase-uhs-sdr25 = <120>, <60>;
157 clk-phase-uhs-ddr50 = <126>, <48>;
158 assigned-clock-rates = <187498123>;
159 bus-width = <4>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_gem3_default>;
166 phy-handle = <&phy0>;
167 phy-mode = "rgmii-id";
168 assigned-clock-rates = <250000000>;
171 #address-cells = <1>;
172 #size-cells = <0>;
174 phy0: ethernet-phy@1 {
175 #phy-cells = <1>;
177 compatible = "ethernet-phy-id2000.a231";
178 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
179 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
180 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
181 ti,dp83867-rxctrl-strap-quirk;
182 reset-assert-us = <100>;
183 reset-deassert-us = <280>;
184 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
192 pinctrl_gpio0_default: gpio0-default {
193 conf {
195 bias-pull-up;
196 power-source = <IO_STANDARD_LVCMOS18>;
204 conf-tx {
206 bias-disable;
207 output-enable;
211 pinctrl_uart1_default: uart1-default {
212 conf {
214 slew-rate = <SLEW_RATE_SLOW>;
215 power-source = <IO_STANDARD_LVCMOS18>;
216 drive-strength = <12>;
219 conf-rx {
221 bias-high-impedance;
224 conf-tx {
226 bias-disable;
227 output-enable;
236 pinctrl_i2c1_default: i2c1-default {
237 conf {
239 bias-pull-up;
240 slew-rate = <SLEW_RATE_SLOW>;
241 power-source = <IO_STANDARD_LVCMOS18>;
250 pinctrl_i2c1_gpio: i2c1-gpio-grp {
251 conf {
253 slew-rate = <SLEW_RATE_SLOW>;
254 power-source = <IO_STANDARD_LVCMOS18>;
263 pinctrl_gem3_default: gem3-default {
264 conf {
266 slew-rate = <SLEW_RATE_SLOW>;
267 power-source = <IO_STANDARD_LVCMOS18>;
270 conf-rx {
272 bias-high-impedance;
273 low-power-disable;
276 conf-bootstrap {
278 bias-disable;
279 output-enable;
280 low-power-disable;
283 conf-tx {
286 bias-disable;
287 output-enable;
288 low-power-enable;
291 conf-mdio {
293 slew-rate = <SLEW_RATE_SLOW>;
294 power-source = <IO_STANDARD_LVCMOS18>;
295 bias-disable;
296 output-enable;
299 mux-mdio {
310 pinctrl_usb0_default: usb0-default {
311 conf {
313 power-source = <IO_STANDARD_LVCMOS18>;
316 conf-rx {
318 bias-high-impedance;
319 drive-strength = <12>;
320 slew-rate = <SLEW_RATE_FAST>;
323 conf-tx {
326 bias-disable;
327 output-enable;
328 drive-strength = <4>;
329 slew-rate = <SLEW_RATE_SLOW>;
338 pinctrl_sdhci1_default: sdhci1-default {
339 conf {
341 slew-rate = <SLEW_RATE_SLOW>;
342 power-source = <IO_STANDARD_LVCMOS18>;
343 bias-disable;
344 output-enable;
347 conf-cd {
349 bias-high-impedance;
350 bias-pull-up;
351 slew-rate = <SLEW_RATE_SLOW>;
352 power-source = <IO_STANDARD_LVCMOS18>;
355 mux-cd {
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_gpio0_default>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_uart1_default>;