Lines Matching +full:output +full:- +full:impedance
1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
21 /dts-v1/;
25 compatible = "xlnx,zynqmp-sk-kv260-revA",
26 "xlnx,zynqmp-sk-kv260-revY",
27 "xlnx,zynqmp-sk-kv260-revZ",
28 "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
31 ina260-u14 {
32 compatible = "iio-hwmon";
33 io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
36 si5332_0: si5332-0 { /* u17 */
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <125000000>;
42 si5332_1: si5332-1 { /* u17 */
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <25000000>;
48 si5332_2: si5332-2 { /* u17 */
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <48000000>;
54 si5332_3: si5332-3 { /* u17 */
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <24000000>;
60 si5332_4: si5332-4 { /* u17 */
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <26000000>;
66 si5332_5: si5332-5 { /* u17 */
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <27000000>;
73 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
74 #address-cells = <1>;
75 #size-cells = <0>;
76 pinctrl-names = "default", "gpio";
77 pinctrl-0 = <&pinctrl_i2c1_default>;
78 pinctrl-1 = <&pinctrl_i2c1_gpio>;
79 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
80 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
84 #io-channel-cells = <1>;
85 label = "ina260-u14";
88 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
96 clock-names = "ref0", "ref1", "ref2";
102 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
103 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
104 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
105 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
106 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
107 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
108 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
109 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
110 phy-names = "sata-phy";
116 phy-names = "dp-phy0", "dp-phy1";
118 assigned-clock-rates = <27000000>, <25000000>, <300000000>;
123 assigned-clock-rates = <600000000>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_usb0_default>;
130 phy-names = "usb3-phy";
132 /* missing usb5744 - u43 */
139 maximum-speed = "super-speed";
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_sdhci1_default>;
151 no-1-8-v;
152 disable-wp;
153 xlnx,mio-bank = <1>;
154 assigned-clock-rates = <187498123>;
155 bus-width = <4>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_gem3_default>;
162 phy-handle = <&phy0>;
163 phy-mode = "rgmii-id";
164 assigned-clock-rates = <250000000>;
167 #address-cells = <1>;
168 #size-cells = <0>;
170 phy0: ethernet-phy@1 {
171 #phy-cells = <1>;
173 compatible = "ethernet-phy-id2000.a231";
174 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
175 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
176 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
177 ti,dp83867-rxctrl-strap-quirk;
178 reset-assert-us = <100>;
179 reset-deassert-us = <280>;
180 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
188 pinctrl_gpio0_default: gpio0-default {
191 bias-pull-up;
192 power-source = <IO_STANDARD_LVCMOS18>;
200 conf-tx {
202 bias-disable;
203 output-enable;
207 pinctrl_uart1_default: uart1-default {
210 slew-rate = <SLEW_RATE_SLOW>;
211 power-source = <IO_STANDARD_LVCMOS18>;
212 drive-strength = <12>;
215 conf-rx {
217 bias-high-impedance;
220 conf-tx {
222 bias-disable;
223 output-enable;
232 pinctrl_i2c1_default: i2c1-default {
235 bias-pull-up;
236 slew-rate = <SLEW_RATE_SLOW>;
237 power-source = <IO_STANDARD_LVCMOS18>;
246 pinctrl_i2c1_gpio: i2c1-gpio-grp {
249 slew-rate = <SLEW_RATE_SLOW>;
250 power-source = <IO_STANDARD_LVCMOS18>;
259 pinctrl_gem3_default: gem3-default {
262 slew-rate = <SLEW_RATE_SLOW>;
263 power-source = <IO_STANDARD_LVCMOS18>;
266 conf-rx {
268 bias-high-impedance;
269 low-power-disable;
272 conf-bootstrap {
274 bias-disable;
275 output-enable;
276 low-power-disable;
279 conf-tx {
282 bias-disable;
283 output-enable;
284 low-power-enable;
287 conf-mdio {
289 slew-rate = <SLEW_RATE_SLOW>;
290 power-source = <IO_STANDARD_LVCMOS18>;
291 bias-disable;
292 output-enable;
295 mux-mdio {
306 pinctrl_usb0_default: usb0-default {
309 power-source = <IO_STANDARD_LVCMOS18>;
312 conf-rx {
314 bias-high-impedance;
315 drive-strength = <12>;
316 slew-rate = <SLEW_RATE_FAST>;
319 conf-tx {
322 bias-disable;
323 output-enable;
324 drive-strength = <4>;
325 slew-rate = <SLEW_RATE_SLOW>;
334 pinctrl_sdhci1_default: sdhci1-default {
337 slew-rate = <SLEW_RATE_SLOW>;
338 power-source = <IO_STANDARD_LVCMOS18>;
339 bias-disable;
340 output-enable;
343 conf-cd {
345 bias-high-impedance;
346 bias-pull-up;
347 slew-rate = <SLEW_RATE_SLOW>;
348 power-source = <IO_STANDARD_LVCMOS18>;
351 mux-cd {
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_gpio0_default>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_uart1_default>;