Lines Matching full:zynqmp_clk
50 zynqmp_clk: clock-controller { label
62 clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
66 clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
70 clocks = <&zynqmp_clk ACPU>;
74 clocks = <&zynqmp_clk DBF_FPD>;
78 clocks = <&zynqmp_clk DBF_FPD>;
82 clocks = <&zynqmp_clk DBF_FPD>;
86 clocks = <&zynqmp_clk DBF_FPD>;
90 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
94 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
98 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
102 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
106 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
110 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
114 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
118 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
122 clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
126 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
130 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
134 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
138 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
142 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
146 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
150 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
154 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
158 clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
162 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
163 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
164 <&zynqmp_clk GEM_TSU>;
165 assigned-clocks = <&zynqmp_clk GEM_TSU>;
169 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
170 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
171 <&zynqmp_clk GEM_TSU>;
172 assigned-clocks = <&zynqmp_clk GEM_TSU>;
176 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
177 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
178 <&zynqmp_clk GEM_TSU>;
179 assigned-clocks = <&zynqmp_clk GEM_TSU>;
183 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
184 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
185 <&zynqmp_clk GEM_TSU>;
186 assigned-clocks = <&zynqmp_clk GEM_TSU>;
190 clocks = <&zynqmp_clk LPD_LSBUS>;
194 clocks = <&zynqmp_clk I2C0_REF>;
198 clocks = <&zynqmp_clk I2C1_REF>;
202 clocks = <&zynqmp_clk PCIE_REF>;
206 clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
210 clocks = <&zynqmp_clk SATA_REF>;
214 clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
215 assigned-clocks = <&zynqmp_clk SDIO0_REF>;
219 clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
220 assigned-clocks = <&zynqmp_clk SDIO1_REF>;
224 clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
228 clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
232 clocks = <&zynqmp_clk LPD_LSBUS>;
236 clocks = <&zynqmp_clk LPD_LSBUS>;
240 clocks = <&zynqmp_clk LPD_LSBUS>;
244 clocks = <&zynqmp_clk LPD_LSBUS>;
248 clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
249 assigned-clocks = <&zynqmp_clk UART0_REF>;
253 clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
254 assigned-clocks = <&zynqmp_clk UART1_REF>;
258 clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
259 assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
263 clocks = <&zynqmp_clk USB3_DUAL_REF>;
267 clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
268 assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
272 clocks = <&zynqmp_clk USB3_DUAL_REF>;
276 clocks = <&zynqmp_clk WDT>;
280 clocks = <&zynqmp_clk LPD_WDT>;
284 clocks = <&zynqmp_clk AMS_REF>;
288 clocks = <&zynqmp_clk DPDMA_REF>;
289 assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
293 clocks = <&zynqmp_clk TOPSW_LSBUS>,
294 <&zynqmp_clk DP_AUDIO_REF>,
295 <&zynqmp_clk DP_VIDEO_REF>;
296 assigned-clocks = <&zynqmp_clk DP_STC_REF>,
297 <&zynqmp_clk DP_AUDIO_REF>,
298 <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */