Lines Matching +full:num +full:- +full:domains
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,j721s2-c71-dsp";
13 reg-names = "l2sram", "l1dram";
15 firmware-name = "j784s4-c71_3-fw";
17 ti,sci-dev-id = <40>;
18 ti,sci-proc-ids = <0x33 0xff>;
23 compatible = "ti,j784s4-pcie-host";
30 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
31 interrupt-names = "link_state";
34 max-link-speed = <3>;
35 num-lanes = <2>;
36 power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>;
38 clock-names = "fck";
39 #address-cells = <3>;
40 #size-cells = <2>;
41 bus-range = <0x0 0xff>;
42 vendor-id = <0x104c>;
43 device-id = <0xb012>;
44 msi-map = <0x0 &gic_its 0x20000 0x10000>;
45 dma-coherent;
46 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
47 ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
52 compatible = "ti,j784s4-pcie-host";
59 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
60 interrupt-names = "link_state";
63 max-link-speed = <3>;
64 num-lanes = <2>;
65 power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>;
67 clock-names = "fck";
68 #address-cells = <3>;
69 #size-cells = <2>;
70 bus-range = <0x0 0xff>;
71 vendor-id = <0x104c>;
72 device-id = <0xb012>;
73 msi-map = <0x0 &gic_its 0x30000 0x10000>;
74 dma-coherent;
75 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
76 ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
81 compatible = "ti,j784s4-wiz-10g";
83 #address-cells = <1>;
84 #size-cells = <1>;
85 power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
87 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
88 assigned-clocks = <&k3_clks 406 6>;
89 assigned-clock-parents = <&k3_clks 406 10>;
90 num-lanes = <4>;
91 #reset-cells = <1>;
92 #clock-cells = <1>;
96 compatible = "ti,j721e-serdes-10g";
98 reg-names = "torrent_phy";
100 reset-names = "torrent_reset";
103 clock-names = "refclk", "phy_en_refclk";
104 assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
107 assigned-clock-parents = <&k3_clks 406 6>,
110 #address-cells = <1>;
111 #size-cells = <0>;
112 #clock-cells = <1>;
119 pcie2_ctrl: pcie2-ctrl@4078 {
120 compatible = "ti,j784s4-pcie-ctrl", "syscon";
124 pcie3_ctrl: pcie3-ctrl@407c {
125 compatible = "ti,j784s4-pcie-ctrl", "syscon";