Lines Matching +full:0 +full:x00004080
16 #clock-cells = <0>;
26 reg = <0x00 0x70000000 0x00 0x800000>;
29 ranges = <0x00 0x00 0x70000000 0x800000>;
31 atf-sram@0 {
32 reg = <0x00 0x20000>;
36 reg = <0x1f0000 0x10000>;
40 reg = <0x200000 0x200000>;
46 reg = <0x00 0x00100000 0x00 0x1c000>;
49 ranges = <0x00 0x00 0x00100000 0x1c000>;
53 reg = <0x4034 0x4>;
59 reg = <0x4044 0x20>;
66 reg = <0x4070 0x4>;
71 reg = <0x4074 0x4>;
76 reg = <0x4078 0x4>;
81 reg = <0x407c 0x4>;
86 reg = <0x00004080 0x30>;
88 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
89 <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */
90 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
91 <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */
92 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
93 <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */
114 reg = <0x4000 0x4>;
116 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */
121 reg = <0x4140 0x18>;
127 reg = <0x82e4 0x4>;
131 #clock-cells = <0>;
137 reg = <0x00 0x3000000 0x00 0x100>;
138 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>;
147 reg = <0x00 0x3010000 0x00 0x100>;
148 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>;
157 reg = <0x00 0x3020000 0x00 0x100>;
158 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>;
167 reg = <0x00 0x3030000 0x00 0x100>;
168 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>;
177 reg = <0x00 0x3040000 0x00 0x100>;
178 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>;
187 reg = <0x00 0x3050000 0x00 0x100>;
188 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>;
202 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
203 <0x00 0x01900000 0x00 0x100000>, /* GICR */
204 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
205 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
206 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
213 reg = <0x00 0x01820000 0x00 0x10000>;
214 socionext,synquacer-pre-its = <0x1000000 0x400000>;
222 reg = <0x00 0x00a00000 0x00 0x800>;
234 /* Proxy 0 addressing */
235 reg = <0x00 0x11c000 0x00 0x120>;
238 pinctrl-single,function-mask = <0xffffffff>;
244 reg = <0x00 0x104200 0x00 0x50>;
247 pinctrl-single,function-mask = <0x00000007>;
253 reg = <0x00 0x104280 0x00 0x20>;
256 pinctrl-single,function-mask = <0x0000001f>;
261 reg = <0x00 0x4e00000 0x00 0x1200>;
265 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
267 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
268 <&main_udmap 0x4a41>;
273 reg = <0x00 0x4e10000 0x00 0x7d>;
280 reg = <0x00 0x2400000 0x00 0x400>;
292 reg = <0x00 0x2410000 0x00 0x400>;
304 reg = <0x00 0x2420000 0x00 0x400>;
316 reg = <0x00 0x2430000 0x00 0x400>;
328 reg = <0x00 0x2440000 0x00 0x400>;
340 reg = <0x00 0x2450000 0x00 0x400>;
352 reg = <0x00 0x2460000 0x00 0x400>;
364 reg = <0x00 0x2470000 0x00 0x400>;
376 reg = <0x00 0x2480000 0x00 0x400>;
388 reg = <0x00 0x2490000 0x00 0x400>;
400 reg = <0x00 0x24a0000 0x00 0x400>;
412 reg = <0x00 0x24b0000 0x00 0x400>;
424 reg = <0x00 0x24c0000 0x00 0x400>;
436 reg = <0x00 0x24d0000 0x00 0x400>;
448 reg = <0x00 0x24e0000 0x00 0x400>;
460 reg = <0x00 0x24f0000 0x00 0x400>;
472 reg = <0x00 0x2500000 0x00 0x400>;
484 reg = <0x00 0x2510000 0x00 0x400>;
496 reg = <0x00 0x2520000 0x00 0x400>;
508 reg = <0x00 0x2530000 0x00 0x400>;
520 reg = <0x00 0x02800000 0x00 0x200>;
522 clocks = <&k3_clks 146 0>;
530 reg = <0x00 0x02810000 0x00 0x200>;
532 clocks = <&k3_clks 388 0>;
540 reg = <0x00 0x02820000 0x00 0x200>;
542 clocks = <&k3_clks 389 0>;
550 reg = <0x00 0x02830000 0x00 0x200>;
552 clocks = <&k3_clks 390 0>;
560 reg = <0x00 0x02840000 0x00 0x200>;
562 clocks = <&k3_clks 391 0>;
570 reg = <0x00 0x02850000 0x00 0x200>;
572 clocks = <&k3_clks 392 0>;
580 reg = <0x00 0x02860000 0x00 0x200>;
582 clocks = <&k3_clks 393 0>;
590 reg = <0x00 0x02870000 0x00 0x200>;
592 clocks = <&k3_clks 394 0>;
600 reg = <0x00 0x02880000 0x00 0x200>;
602 clocks = <&k3_clks 395 0>;
610 reg = <0x00 0x02890000 0x00 0x200>;
612 clocks = <&k3_clks 396 0>;
620 reg = <0x00 0x00600000 0x00 0x100>;
628 ti,davinci-gpio-unbanked = <0>;
630 clocks = <&k3_clks 163 0>;
637 reg = <0x00 0x00610000 0x00 0x100>;
645 ti,davinci-gpio-unbanked = <0>;
647 clocks = <&k3_clks 164 0>;
654 reg = <0x00 0x00620000 0x00 0x100>;
662 ti,davinci-gpio-unbanked = <0>;
664 clocks = <&k3_clks 165 0>;
671 reg = <0x00 0x00630000 0x00 0x100>;
679 ti,davinci-gpio-unbanked = <0>;
681 clocks = <&k3_clks 166 0>;
689 reg = <0x00 0x4104000 0x00 0x100>;
705 reg = <0x00 0x6000000 0x00 0x10000>,
706 <0x00 0x6010000 0x00 0x10000>,
707 <0x00 0x6020000 0x00 0x10000>;
709 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
711 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
720 reg = <0x00 0x02000000 0x00 0x100>;
723 #size-cells = <0>;
732 reg = <0x00 0x02010000 0x00 0x100>;
735 #size-cells = <0>;
744 reg = <0x00 0x02020000 0x00 0x100>;
747 #size-cells = <0>;
756 reg = <0x00 0x02030000 0x00 0x100>;
759 #size-cells = <0>;
768 reg = <0x00 0x02040000 0x00 0x100>;
771 #size-cells = <0>;
780 reg = <0x00 0x02050000 0x00 0x100>;
783 #size-cells = <0>;
792 reg = <0x00 0x02060000 0x00 0x100>;
795 #size-cells = <0>;
804 reg = <0x00 0x04500000 0x00 0x00001000>;
808 dmas = <&main_bcdma_csi 0 0x4940 0>;
815 reg = <0x00 0x04504000 0x00 0x00001000>;
816 clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>,
825 #size-cells = <0>;
827 csi0_port0: port@0 {
828 reg = <0>;
857 reg = <0x00 0x04510000 0x00 0x1000>;
861 dmas = <&main_bcdma_csi 0 0x4960 0>;
868 reg = <0x00 0x04514000 0x00 0x00001000>;
869 clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>,
877 #size-cells = <0>;
879 csi1_port0: port@0 {
880 reg = <0>;
909 reg = <0x00 0x04520000 0x00 0x00001000>;
913 dmas = <&main_bcdma_csi 0 0x4980 0>;
920 reg = <0x00 0x04524000 0x00 0x00001000>;
921 clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>,
930 #size-cells = <0>;
932 csi2_port0: port@0 {
933 reg = <0>;
962 reg = <0x00 0x04580000 0x00 0x00001100>;
963 #phy-cells = <0>;
970 reg = <0x00 0x04590000 0x00 0x00001100>;
971 #phy-cells = <0>;
978 reg = <0x00 0x045a0000 0x00 0x00001100>;
979 #phy-cells = <0>;
986 reg = <0x00 0x4210000 0x00 0x10000>;
994 reg = <0x00 0x4220000 0x00 0x10000>;
1002 reg = <0x00 0x04f80000 0x00 0x1000>,
1003 <0x00 0x04f88000 0x00 0x400>;
1011 ti,otap-del-sel-legacy = <0x0>;
1012 ti,otap-del-sel-mmc-hs = <0x0>;
1013 ti,otap-del-sel-ddr52 = <0x6>;
1014 ti,otap-del-sel-hs200 = <0x8>;
1015 ti,otap-del-sel-hs400 = <0x5>;
1016 ti,itap-del-sel-legacy = <0x10>;
1017 ti,itap-del-sel-mmc-hs = <0xa>;
1018 ti,strobe-sel = <0x77>;
1019 ti,clkbuf-sel = <0x7>;
1020 ti,trm-icp = <0x8>;
1030 reg = <0x00 0x04fb0000 0x00 0x1000>,
1031 <0x00 0x04fb8000 0x00 0x400>;
1039 ti,otap-del-sel-legacy = <0x0>;
1040 ti,otap-del-sel-sd-hs = <0x0>;
1041 ti,otap-del-sel-sdr12 = <0xf>;
1042 ti,otap-del-sel-sdr25 = <0xf>;
1043 ti,otap-del-sel-sdr50 = <0xc>;
1044 ti,otap-del-sel-sdr104 = <0x5>;
1045 ti,otap-del-sel-ddr50 = <0xc>;
1046 ti,itap-del-sel-legacy = <0x0>;
1047 ti,itap-del-sel-sd-hs = <0x0>;
1048 ti,itap-del-sel-sdr12 = <0x0>;
1049 ti,itap-del-sel-sdr25 = <0x0>;
1050 ti,itap-del-sel-ddr50 = <0x2>;
1051 ti,clkbuf-sel = <0x7>;
1052 ti,trm-icp = <0x8>;
1059 reg = <0x00 0x02900000 0x00 0x1000>,
1060 <0x00 0x02907000 0x00 0x400>,
1061 <0x00 0x0d000000 0x00 0x00800000>,
1062 <0x00 0x10000000 0x00 0x00001000>;
1067 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
1071 clocks = <&k3_clks 332 0>;
1075 bus-range = <0x0 0xff>;
1076 vendor-id = <0x104c>;
1077 device-id = <0xb012>;
1078 msi-map = <0x0 &gic_its 0x0 0x10000>;
1080 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
1081 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
1082 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1088 reg = <0x00 0x02910000 0x00 0x1000>,
1089 <0x00 0x02917000 0x00 0x400>,
1090 <0x00 0x0d800000 0x00 0x00800000>,
1091 <0x00 0x18000000 0x00 0x00001000>;
1096 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
1100 clocks = <&k3_clks 333 0>;
1104 bus-range = <0x0 0xff>;
1105 vendor-id = <0x104c>;
1106 device-id = <0xb012>;
1107 msi-map = <0x0 &gic_its 0x10000 0x10000>;
1109 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
1110 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
1111 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1117 reg = <0x00 0x02920000 0x00 0x1000>,
1118 <0x00 0x02927000 0x00 0x400>,
1119 <0x00 0x0e000000 0x00 0x00800000>,
1120 <0x44 0x00000000 0x00 0x00001000>;
1125 ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
1129 clocks = <&k3_clks 334 0>;
1133 bus-range = <0x0 0xff>;
1134 vendor-id = <0x104c>;
1135 device-id = <0xb012>;
1136 msi-map = <0x0 &gic_its 0x20000 0x10000>;
1138 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
1139 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
1140 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1146 reg = <0x00 0x02930000 0x00 0x1000>,
1147 <0x00 0x02937000 0x00 0x400>,
1148 <0x00 0x0e800000 0x00 0x00800000>,
1149 <0x44 0x10000000 0x00 0x00001000>;
1154 ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
1158 clocks = <&k3_clks 335 0>;
1162 bus-range = <0x0 0xff>;
1163 vendor-id = <0x104c>;
1164 device-id = <0xb012>;
1165 msi-map = <0x0 &gic_its 0x30000 0x10000>;
1167 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
1168 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
1169 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1185 ranges = <0x5060000 0x00 0x5060000 0x10000>;
1190 reg = <0x05060000 0x010000>;
1192 resets = <&serdes_wiz0 0>;
1204 #size-cells = <0>;
1222 ranges = <0x05070000 0x00 0x05070000 0x10000>;
1227 reg = <0x05070000 0x010000>;
1229 resets = <&serdes_wiz1 0>;
1241 #size-cells = <0>;
1259 ranges = <0x05020000 0x00 0x05020000 0x10000>;
1264 reg = <0x05020000 0x010000>;
1266 resets = <&serdes_wiz2 0>;
1278 #size-cells = <0>;
1296 ranges = <0x05050000 0x00 0x05050000 0x10000>,
1297 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
1306 reg = <0x05050000 0x010000>,
1307 <0x0a030a00 0x40>; /* DPTX PHY */
1309 resets = <&serdes_wiz4 0>;
1321 #size-cells = <0>;
1332 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
1339 reg = <0x00 0x310e0000 0x00 0x4000>;
1346 ti,interrupt-ranges = <0 64 64>,
1353 reg = <0x00 0x33d00000 0x00 0x100000>;
1355 #interrupt-cells = <0>;
1360 ti,interrupt-ranges = <0 0 256>;
1369 reg = <0x00 0x32c00000 0x00 0x100000>,
1370 <0x00 0x32400000 0x00 0x100000>,
1371 <0x00 0x32800000 0x00 0x100000>;
1378 reg = <0x00 0x30e00000 0x00 0x1000>;
1384 reg = <0x00 0x31f80000 0x00 0x200>;
1394 reg = <0x00 0x31f81000 0x00 0x200>;
1404 reg = <0x00 0x31f82000 0x00 0x200>;
1414 reg = <0x00 0x31f83000 0x00 0x200>;
1424 reg = <0x00 0x31f84000 0x00 0x200>;
1434 reg = <0x00 0x31f85000 0x00 0x200>;
1444 reg = <0x00 0x31f86000 0x00 0x200>;
1454 reg = <0x00 0x31f87000 0x00 0x200>;
1464 reg = <0x00 0x31f88000 0x00 0x200>;
1474 reg = <0x00 0x31f89000 0x00 0x200>;
1484 reg = <0x00 0x31f8a000 0x00 0x200>;
1494 reg = <0x00 0x31f8b000 0x00 0x200>;
1504 reg = <0x00 0x31f90000 0x00 0x200>;
1514 reg = <0x00 0x31f91000 0x00 0x200>;
1524 reg = <0x00 0x31f92000 0x00 0x200>;
1534 reg = <0x00 0x31f93000 0x00 0x200>;
1544 reg = <0x00 0x31f94000 0x00 0x200>;
1554 reg = <0x00 0x31f95000 0x00 0x200>;
1564 reg = <0x00 0x31f96000 0x00 0x200>;
1574 reg = <0x00 0x31f97000 0x00 0x200>;
1584 reg = <0x00 0x31f98000 0x00 0x200>;
1594 reg = <0x00 0x31f99000 0x00 0x200>;
1604 reg = <0x00 0x31f9a000 0x00 0x200>;
1614 reg = <0x00 0x31f9b000 0x00 0x200>;
1624 reg = <0x00 0x3c000000 0x00 0x400000>,
1625 <0x00 0x38000000 0x00 0x400000>,
1626 <0x00 0x31120000 0x00 0x100>,
1627 <0x00 0x33000000 0x00 0x40000>,
1628 <0x00 0x31080000 0x00 0x40000>;
1631 ti,sci-rm-range-gp-rings = <0x1>;
1639 reg = <0x00 0x31150000 0x00 0x100>,
1640 <0x00 0x34000000 0x00 0x80000>,
1641 <0x00 0x35000000 0x00 0x200000>,
1642 <0x00 0x30b00000 0x00 0x20000>,
1643 <0x00 0x30c00000 0x00 0x8000>,
1644 <0x00 0x30d00000 0x00 0x4000>;
1654 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1655 <0x0f>, /* TX_HCHAN */
1656 <0x10>; /* TX_UHCHAN */
1657 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1658 <0x0b>, /* RX_HCHAN */
1659 <0x0c>; /* RX_UHCHAN */
1660 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1665 reg = <0x00 0x311a0000 0x00 0x100>,
1666 <0x00 0x35d00000 0x00 0x20000>,
1667 <0x00 0x35c00000 0x00 0x10000>,
1668 <0x00 0x35e00000 0x00 0x80000>;
1674 ti,sci-rm-range-rchan = <0x21>;
1675 ti,sci-rm-range-tchan = <0x22>;
1680 reg = <0x00 0x310d0000 0x00 0x400>;
1682 clocks = <&k3_clks 282 0>;
1695 reg = <0x00 0xc000000 0x00 0x200000>;
1697 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
1701 clocks = <&k3_clks 64 0>;
1705 dmas = <&main_udmap 0xca00>,
1706 <&main_udmap 0xca01>,
1707 <&main_udmap 0xca02>,
1708 <&main_udmap 0xca03>,
1709 <&main_udmap 0xca04>,
1710 <&main_udmap 0xca05>,
1711 <&main_udmap 0xca06>,
1712 <&main_udmap 0xca07>,
1713 <&main_udmap 0x4a00>;
1722 #size-cells = <0>;
1783 reg = <0x00 0xf00 0x00 0x100>;
1785 #size-cells = <0>;
1786 clocks = <&k3_clks 64 0>;
1794 reg = <0x00 0x3d000 0x00 0x400>;
1806 reg = <0x00 0xc200000 0x00 0x200000>;
1808 ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>;
1812 clocks = <&k3_clks 62 0>;
1816 dmas = <&main_udmap 0xc640>,
1817 <&main_udmap 0xc641>,
1818 <&main_udmap 0xc642>,
1819 <&main_udmap 0xc643>,
1820 <&main_udmap 0xc644>,
1821 <&main_udmap 0xc645>,
1822 <&main_udmap 0xc646>,
1823 <&main_udmap 0xc647>,
1824 <&main_udmap 0x4640>;
1833 #size-cells = <0>;
1846 reg = <0x00 0xf00 0x00 0x100>;
1848 #size-cells = <0>;
1849 clocks = <&k3_clks 62 0>;
1857 reg = <0x00 0x3d000 0x00 0x400>;
1869 reg = <0x00 0x02701000 0x00 0x200>,
1870 <0x00 0x02708000 0x00 0x8000>;
1878 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1884 reg = <0x00 0x02711000 0x00 0x200>,
1885 <0x00 0x02718000 0x00 0x8000>;
1893 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1899 reg = <0x00 0x02721000 0x00 0x200>,
1900 <0x00 0x02728000 0x00 0x8000>;
1908 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1914 reg = <0x00 0x02731000 0x00 0x200>,
1915 <0x00 0x02738000 0x00 0x8000>;
1923 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1929 reg = <0x00 0x02741000 0x00 0x200>,
1930 <0x00 0x02748000 0x00 0x8000>;
1938 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1944 reg = <0x00 0x02751000 0x00 0x200>,
1945 <0x00 0x02758000 0x00 0x8000>;
1953 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1959 reg = <0x00 0x02761000 0x00 0x200>,
1960 <0x00 0x02768000 0x00 0x8000>;
1968 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1974 reg = <0x00 0x02771000 0x00 0x200>,
1975 <0x00 0x02778000 0x00 0x8000>;
1983 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1989 reg = <0x00 0x02781000 0x00 0x200>,
1990 <0x00 0x02788000 0x00 0x8000>;
1998 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2004 reg = <0x00 0x02791000 0x00 0x200>,
2005 <0x00 0x02798000 0x00 0x8000>;
2013 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2019 reg = <0x00 0x027a1000 0x00 0x200>,
2020 <0x00 0x027a8000 0x00 0x8000>;
2028 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2034 reg = <0x00 0x027b1000 0x00 0x200>,
2035 <0x00 0x027b8000 0x00 0x8000>;
2043 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2049 reg = <0x00 0x027c1000 0x00 0x200>,
2050 <0x00 0x027c8000 0x00 0x8000>;
2058 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2064 reg = <0x00 0x027d1000 0x00 0x200>,
2065 <0x00 0x027d8000 0x00 0x8000>;
2073 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2079 reg = <0x00 0x02681000 0x00 0x200>,
2080 <0x00 0x02688000 0x00 0x8000>;
2088 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2094 reg = <0x00 0x02691000 0x00 0x200>,
2095 <0x00 0x02698000 0x00 0x8000>;
2103 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2109 reg = <0x00 0x026a1000 0x00 0x200>,
2110 <0x00 0x026a8000 0x00 0x8000>;
2118 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2124 reg = <0x00 0x026b1000 0x00 0x200>,
2125 <0x00 0x026b8000 0x00 0x8000>;
2133 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2139 reg = <0x00 0x02100000 0x00 0x400>;
2142 #size-cells = <0>;
2150 reg = <0x00 0x02110000 0x00 0x400>;
2153 #size-cells = <0>;
2161 reg = <0x00 0x02120000 0x00 0x400>;
2164 #size-cells = <0>;
2172 reg = <0x00 0x02130000 0x00 0x400>;
2175 #size-cells = <0>;
2183 reg = <0x00 0x02140000 0x00 0x400>;
2186 #size-cells = <0>;
2194 reg = <0x00 0x02150000 0x00 0x400>;
2197 #size-cells = <0>;
2205 reg = <0x00 0x02160000 0x00 0x400>;
2208 #size-cells = <0>;
2216 reg = <0x00 0x02170000 0x00 0x400>;
2219 #size-cells = <0>;
2227 reg = <0x00 0x4e80000 0x00 0x100>;
2239 reg = <0x00 0x4e84000 0x00 0x10000>;
2254 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
2255 <0x5d00000 0x00 0x5d00000 0x20000>;
2260 reg = <0x5c00000 0x00010000>,
2261 <0x5c10000 0x00010000>;
2265 ti,sci-proc-ids = <0x06 0xff>;
2275 reg = <0x5d00000 0x00010000>,
2276 <0x5d10000 0x00010000>;
2280 ti,sci-proc-ids = <0x07 0xff>;
2294 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
2295 <0x5f00000 0x00 0x5f00000 0x20000>;
2300 reg = <0x5e00000 0x00010000>,
2301 <0x5e10000 0x00010000>;
2305 ti,sci-proc-ids = <0x08 0xff>;
2315 reg = <0x5f00000 0x00010000>,
2316 <0x5f10000 0x00010000>;
2320 ti,sci-proc-ids = <0x09 0xff>;
2334 ranges = <0x5900000 0x00 0x5900000 0x20000>,
2335 <0x5a00000 0x00 0x5a00000 0x20000>;
2340 reg = <0x5900000 0x00010000>,
2341 <0x5910000 0x00010000>;
2345 ti,sci-proc-ids = <0x0a 0xff>;
2355 reg = <0x5a00000 0x00010000>,
2356 <0x5a10000 0x00010000>;
2360 ti,sci-proc-ids = <0x0b 0xff>;
2371 reg = <0x00 0x64800000 0x00 0x00080000>,
2372 <0x00 0x64e00000 0x00 0x0000c000>;
2376 ti,sci-proc-ids = <0x30 0xff>;
2384 reg = <0x00 0x65800000 0x00 0x00080000>,
2385 <0x00 0x65e00000 0x00 0x0000c000>;
2389 ti,sci-proc-ids = <0x31 0xff>;
2397 reg = <0x00 0x66800000 0x00 0x00080000>,
2398 <0x00 0x66e00000 0x00 0x0000c000>;
2402 ti,sci-proc-ids = <0x32 0xff>;
2410 reg = <0x00 0x67800000 0x00 0x00080000>,
2411 <0x00 0x67e00000 0x00 0x0000c000>;
2415 ti,sci-proc-ids = <0x33 0xff>;
2423 reg = <0x00 0x700000 0x00 0x1000>;
2431 reg = <0x00 0x2200000 0x00 0x100>;
2432 clocks = <&k3_clks 348 0>;
2434 assigned-clocks = <&k3_clks 348 0>;
2440 reg = <0x00 0x2210000 0x00 0x100>;
2441 clocks = <&k3_clks 349 0>;
2443 assigned-clocks = <&k3_clks 349 0>;
2449 reg = <0x00 0x2220000 0x00 0x100>;
2450 clocks = <&k3_clks 350 0>;
2452 assigned-clocks = <&k3_clks 350 0>;
2458 reg = <0x00 0x2230000 0x00 0x100>;
2459 clocks = <&k3_clks 351 0>;
2461 assigned-clocks = <&k3_clks 351 0>;
2467 reg = <0x00 0x2240000 0x00 0x100>;
2468 clocks = <&k3_clks 352 0>;
2470 assigned-clocks = <&k3_clks 352 0>;
2476 reg = <0x00 0x2250000 0x00 0x100>;
2477 clocks = <&k3_clks 353 0>;
2479 assigned-clocks = <&k3_clks 353 0>;
2485 reg = <0x00 0x2260000 0x00 0x100>;
2486 clocks = <&k3_clks 354 0>;
2488 assigned-clocks = <&k3_clks 354 0>;
2494 reg = <0x00 0x2270000 0x00 0x100>;
2495 clocks = <&k3_clks 355 0>;
2497 assigned-clocks = <&k3_clks 355 0>;
2508 reg = <0x00 0x22f0000 0x00 0x100>;
2509 clocks = <&k3_clks 360 0>;
2511 assigned-clocks = <&k3_clks 360 0>;
2519 reg = <0x00 0x2300000 0x00 0x100>;
2520 clocks = <&k3_clks 356 0>;
2522 assigned-clocks = <&k3_clks 356 0>;
2530 reg = <0x00 0x2310000 0x00 0x100>;
2531 clocks = <&k3_clks 357 0>;
2533 assigned-clocks = <&k3_clks 357 0>;
2541 reg = <0x00 0x2320000 0x00 0x100>;
2542 clocks = <&k3_clks 358 0>;
2544 assigned-clocks = <&k3_clks 358 0>;
2552 reg = <0x00 0x2330000 0x00 0x100>;
2553 clocks = <&k3_clks 359 0>;
2555 assigned-clocks = <&k3_clks 359 0>;
2563 reg = <0x00 0x23c0000 0x00 0x100>;
2564 clocks = <&k3_clks 361 0>;
2566 assigned-clocks = <&k3_clks 361 0>;
2574 reg = <0x00 0x23d0000 0x00 0x100>;
2575 clocks = <&k3_clks 362 0>;
2577 assigned-clocks = <&k3_clks 362 0>;
2585 reg = <0x00 0x23e0000 0x00 0x100>;
2586 clocks = <&k3_clks 363 0>;
2588 assigned-clocks = <&k3_clks 363 0>;
2596 reg = <0x00 0x23f0000 0x00 0x100>;
2597 clocks = <&k3_clks 364 0>;
2599 assigned-clocks = <&k3_clks 364 0>;
2607 reg = <0x00 0x2540000 0x00 0x100>;
2608 clocks = <&k3_clks 365 0>;
2610 assigned-clocks = <&k3_clks 365 0>;
2618 reg = <0x00 0x2550000 0x00 0x100>;
2619 clocks = <&k3_clks 366 0>;
2621 assigned-clocks = <&k3_clks 366 0>;
2629 reg = <0x0 0xa000000 0x0 0x30a00>,
2630 <0x0 0x4f40000 0x0 0x20>;
2640 #size-cells = <0>;
2649 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
2650 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
2651 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
2652 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
2653 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
2654 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
2655 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
2656 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
2657 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
2658 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
2659 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
2660 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
2661 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
2662 <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */
2663 <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */
2664 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
2665 <0x00 0x04af0000 0x00 0x10000>; /* wb */
2672 clocks = <&k3_clks 218 0>,
2698 reg = <0x00 0x02b00000 0x00 0x2000>,
2699 <0x00 0x02b08000 0x00 0x1000>;
2704 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
2706 clocks = <&k3_clks 265 0>;
2708 assigned-clocks = <&k3_clks 265 0>;
2716 reg = <0x00 0x02b10000 0x00 0x2000>,
2717 <0x00 0x02b18000 0x00 0x1000>;
2722 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
2724 clocks = <&k3_clks 266 0>;
2726 assigned-clocks = <&k3_clks 266 0>;
2734 reg = <0x00 0x02b20000 0x00 0x2000>,
2735 <0x00 0x02b28000 0x00 0x1000>;
2740 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
2742 clocks = <&k3_clks 267 0>;
2744 assigned-clocks = <&k3_clks 267 0>;
2752 reg = <0x00 0x02b30000 0x00 0x2000>,
2753 <0x00 0x02b38000 0x00 0x1000>;
2758 dmas = <&main_udmap 0xc403>, <&main_udmap 0x4403>;
2760 clocks = <&k3_clks 268 0>;
2762 assigned-clocks = <&k3_clks 268 0>;
2770 reg = <0x00 0x02b40000 0x00 0x2000>,
2771 <0x00 0x02b48000 0x00 0x1000>;
2776 dmas = <&main_udmap 0xc404>, <&main_udmap 0x4404>;
2778 clocks = <&k3_clks 269 0>;
2780 assigned-clocks = <&k3_clks 269 0>;