Lines Matching +full:btcm +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clk-0 {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <0>;
21 compatible = "ti,am64-wiz-10g";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
27 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
28 num-lanes = <1>;
29 #reset-cells = <1>;
30 #clock-cells = <1>;
32 assigned-clocks = <&k3_clks 279 1>;
33 assigned-clock-parents = <&k3_clks 279 5>;
36 compatible = "ti,j721e-serdes-10g";
38 reg-names = "torrent_phy";
40 reset-names = "torrent_reset";
43 clock-names = "refclk", "phy_en_refclk";
44 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
47 assigned-clock-parents = <&k3_clks 279 1>,
50 #address-cells = <1>;
51 #size-cells = <0>;
52 #clock-cells = <1>;
59 compatible = "ti,am64-wiz-10g";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
65 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
66 num-lanes = <1>;
67 #reset-cells = <1>;
68 #clock-cells = <1>;
70 assigned-clocks = <&k3_clks 280 1>;
71 assigned-clock-parents = <&k3_clks 280 5>;
74 compatible = "ti,j721e-serdes-10g";
76 reg-names = "torrent_phy";
78 reset-names = "torrent_reset";
81 clock-names = "refclk", "phy_en_refclk";
82 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
85 assigned-clock-parents = <&k3_clks 280 1>,
88 #address-cells = <1>;
89 #size-cells = <0>;
90 #clock-cells = <1>;
97 compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
102 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
105 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
106 interrupt-names = "link_state";
109 max-link-speed = <3>;
110 num-lanes = <1>;
111 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
113 clock-names = "fck", "pcie_refclk";
114 #address-cells = <3>;
115 #size-cells = <2>;
116 bus-range = <0x0 0xff>;
117 vendor-id = <0x104c>;
118 device-id = <0xb010>;
119 cdns,no-bar-match-nbits = <64>;
120 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
121 msi-map = <0x0 &gic_its 0x0 0x10000>;
126 compatible = "ti,j721e-usb";
128 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
130 clock-names = "ref", "lpm";
131 assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
132 assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
133 #address-cells = <2>;
134 #size-cells = <2>;
143 reg-names = "otg",
149 interrupt-names = "host",
152 maximum-speed = "super-speed";
158 compatible = "ti,j721e-csi2rx-shim";
161 #address-cells = <2>;
162 #size-cells = <2>;
164 dma-names = "rx0";
165 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
168 cdns_csi2rx1: csi-bridge@30121000 {
169 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
173 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
176 phy-names = "dphy";
179 #address-cells = <1>;
180 #size-cells = <0>;
211 compatible = "ti,j721e-csi2rx-shim";
214 #address-cells = <2>;
215 #size-cells = <2>;
216 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
218 dma-names = "rx0";
221 cdns_csi2rx2: csi-bridge@30141000 {
222 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
226 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
229 phy-names = "dphy";
232 #address-cells = <1>;
233 #size-cells = <0>;
264 compatible = "ti,j721e-csi2rx-shim";
267 #address-cells = <2>;
268 #size-cells = <2>;
270 dma-names = "rx0";
271 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
274 cdns_csi2rx3: csi-bridge@30161000 {
275 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
279 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
282 phy-names = "dphy";
285 #address-cells = <1>;
286 #size-cells = <0>;
317 compatible = "cdns,dphy-rx";
319 #phy-cells = <0>;
320 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>;
325 compatible = "cdns,dphy-rx";
327 #phy-cells = <0>;
328 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
333 compatible = "cdns,dphy-rx";
335 #phy-cells = <0>;
336 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
341 compatible = "ti,am62-r5fss";
342 #address-cells = <1>;
343 #size-cells = <1>;
346 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
350 compatible = "ti,am62-r5f";
353 reg-names = "atcm", "btcm";
355 firmware-name = "j722s-main-r5f0_0-fw";
357 ti,sci-dev-id = <262>;
358 ti,sci-proc-ids = <0x04 0xff>;
359 ti,atcm-enable = <1>;
360 ti,btcm-enable = <1>;
366 compatible = "ti,am62a-c7xv-dsp";
368 reg-names = "l2sram";
370 firmware-name = "j722s-c71_0-fw";
372 ti,sci-dev-id = <208>;
373 ti,sci-proc-ids = <0x30 0xff>;
378 compatible = "ti,am62a-c7xv-dsp";
380 reg-names = "l2sram";
382 firmware-name = "j722s-c71_1-fw";
384 ti,sci-dev-id = <268>;
385 ti,sci-proc-ids = <0x31 0xff>;
391 compatible = "ti,j722s-dmss-bcdma-csi";
396 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
397 ti,sci-rm-range-tchan = <0x22>;
403 firmware-name = "j722s-mcu-r5f0_0-fw";
409 firmware-name = "j722s-wkup-r5f0_0-fw";
413 serdes_ln_ctrl: mux-controller@4080 {
414 compatible = "reg-mux";
416 #mux-control-cells = <1>;
417 mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
422 compatible = "ti,am62-audio-refclk";
425 assigned-clocks = <&k3_clks 157 18>;
426 assigned-clock-parents = <&k3_clks 157 33>;
427 #clock-cells = <0>;
432 pcie0_ctrl: pcie0-ctrl@4070 {
433 compatible = "ti,j784s4-pcie-ctrl", "syscon";
444 ti,interrupt-ranges = <7 71 21>;
448 gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
454 gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>,
456 gpio-reserved-ranges = <0 7>, <32 10>;