Lines Matching +full:1 +full:f000000
20 serdes_wiz0: phy@f000000 {
23 #address-cells = <1>;
24 #size-cells = <1>;
26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
28 num-lanes = <1>;
29 #reset-cells = <1>;
30 #clock-cells = <1>;
32 assigned-clocks = <&k3_clks 279 1>;
37 serdes0: serdes@f000000 {
49 assigned-clock-parents = <&k3_clks 279 1>,
50 <&k3_clks 279 1>,
51 <&k3_clks 279 1>;
52 #address-cells = <1>;
54 #clock-cells = <1>;
61 #address-cells = <1>;
62 #size-cells = <1>;
64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
66 num-lanes = <1>;
67 #reset-cells = <1>;
68 #clock-cells = <1>;
70 assigned-clocks = <&k3_clks 280 1>;
87 assigned-clock-parents = <&k3_clks 280 1>,
88 <&k3_clks 280 1>,
89 <&k3_clks 280 1>;
90 #address-cells = <1>;
92 #clock-cells = <1>;
103 ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
104 …0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
110 num-lanes = <1>;
129 clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
179 #address-cells = <1>;
187 csi1_port1: port@1 {
188 reg = <1>;
232 #address-cells = <1>;
240 csi2_port1: port@1 {
241 reg = <1>;
285 #address-cells = <1>;
293 csi3_port1: port@1 {
294 reg = <1>;
342 #address-cells = <1>;
343 #size-cells = <1>;
354 resets = <&k3_reset 262 1>;
359 ti,atcm-enable = <1>;
360 ti,btcm-enable = <1>;
361 ti,loczrama = <1>;
369 resets = <&k3_reset 208 1>;
381 resets = <&k3_reset 268 1>;
416 #mux-control-cells = <1>;