Lines Matching +full:0 +full:x68000000
12 serdes_refclk: clk-0 {
14 #clock-cells = <0>;
15 clock-frequency = <0>;
22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
39 reg = <0x0f000000 0x00010000>;
41 resets = <&serdes_wiz0 0>;
53 #size-cells = <0>;
60 ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
77 reg = <0x0f010000 0x00010000>;
79 resets = <&serdes_wiz1 0>;
91 #size-cells = <0>;
98 reg = <0x00 0x0f102000 0x00 0x1000>,
99 <0x00 0x0f100000 0x00 0x400>,
100 <0x00 0x0d000000 0x00 0x00800000>,
101 <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
103 ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
104 <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
105 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
112 clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
116 bus-range = <0x0 0xff>;
117 vendor-id = <0x104c>;
118 device-id = <0xb010>;
120 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
121 msi-map = <0x0 &gic_its 0x0 0x10000>;
127 reg = <0x00 0x0f920000 0x00 0x100>;
140 reg = <0x00 0x31200000 0x00 0x10000>,
141 <0x00 0x31210000 0x00 0x10000>,
142 <0x00 0x31220000 0x00 0x10000>;
146 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
159 reg = <0x00 0x30122000 0x00 0x1000>;
163 dmas = <&main_bcdma_csi 0 0x5100 0>;
170 reg = <0x00 0x30121000 0x00 0x1000>;
171 clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>,
172 <&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>;
180 #size-cells = <0>;
182 csi1_port0: port@0 {
183 reg = <0>;
212 reg = <0x00 0x30142000 0x00 0x1000>;
217 dmas = <&main_bcdma_csi 0 0x5200 0>;
223 reg = <0x00 0x30141000 0x00 0x1000>;
224 clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>,
225 <&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>;
233 #size-cells = <0>;
235 csi2_port0: port@0 {
236 reg = <0>;
265 reg = <0x00 0x30162000 0x00 0x1000>;
269 dmas = <&main_bcdma_csi 0 0x5300 0>;
276 reg = <0x00 0x30161000 0x00 0x1000>;
277 clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>,
278 <&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>;
286 #size-cells = <0>;
288 csi3_port0: port@0 {
289 reg = <0>;
318 reg = <0x00 0x30130000 0x00 0x1100>;
319 #phy-cells = <0>;
326 reg = <0x00 0x30150000 0x00 0x1100>;
327 #phy-cells = <0>;
334 reg = <0x00 0x30170000 0x00 0x1100>;
335 #phy-cells = <0>;
344 ranges = <0x78400000 0x00 0x78400000 0x8000>,
345 <0x78500000 0x00 0x78500000 0x8000>;
351 reg = <0x78400000 0x00008000>,
352 <0x78500000 0x00008000>;
358 ti,sci-proc-ids = <0x04 0xff>;
367 reg = <0x00 0x7e000000 0x00 0x00200000>;
373 ti,sci-proc-ids = <0x30 0xff>;
379 reg = <0x00 0x7e200000 0x00 0x00200000>;
385 ti,sci-proc-ids = <0x31 0xff>;
392 reg = <0x00 0x4e230000 0x00 0x100>,
393 <0x00 0x4e180000 0x00 0x20000>,
394 <0x00 0x4e300000 0x00 0x10000>,
395 <0x00 0x4e100000 0x00 0x80000>;
397 ti,sci-rm-range-tchan = <0x22>;
415 reg = <0x4080 0x14>;
417 mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
418 <0x10 0x3>; /* SERDES1 lane0 select */
423 reg = <0x82e0 0x4>;
424 clocks = <&k3_clks 157 0>;
425 assigned-clocks = <&k3_clks 157 0>;
427 #clock-cells = <0>;
432 reg = <0x82e4 0x4>;
436 #clock-cells = <0>;
443 reg = <0x4070 0x4>;
448 reg = <0x00 0x70000000 0x00 0x40000>;
449 ranges = <0x00 0x00 0x70000000 0x40000>;
457 gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
465 gpio-reserved-ranges = <0 7>, <32 10>;