Lines Matching +full:gpio +full:- +full:7 +full:- +full:segment
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/ti,sci_pm_domain.h>
15 #include "k3-pinctrl.h"
21 interrupt-parent = <&gic500>;
22 #address-cells = <2>;
23 #size-cells = <2>;
28 #address-cells = <1>;
29 #size-cells = <0>;
30 cpu-map {
43 compatible = "arm,cortex-a72";
46 enable-method = "psci";
47 i-cache-size = <0xc000>;
48 i-cache-line-size = <64>;
49 i-cache-sets = <256>;
50 d-cache-size = <0x8000>;
51 d-cache-line-size = <64>;
52 d-cache-sets = <256>;
53 next-level-cache = <&L2_0>;
57 compatible = "arm,cortex-a72";
60 enable-method = "psci";
61 i-cache-size = <0xc000>;
62 i-cache-line-size = <64>;
63 i-cache-sets = <256>;
64 d-cache-size = <0x8000>;
65 d-cache-line-size = <64>;
66 d-cache-sets = <256>;
67 next-level-cache = <&L2_0>;
71 L2_0: l2-cache0 {
73 cache-unified;
74 cache-level = <2>;
75 cache-size = <0x100000>;
76 cache-line-size = <64>;
77 cache-sets = <1024>;
78 next-level-cache = <&msmc_l3>;
81 msmc_l3: l3-cache0 {
83 cache-level = <3>;
84 cache-unified;
89 compatible = "linaro,optee-tz";
94 compatible = "arm,psci-1.0";
99 a72_timer0: timer-cl0-cpu0 {
100 compatible = "arm,armv8-timer";
109 compatible = "arm,cortex-a72-pmu";
111 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
115 compatible = "simple-bus";
116 #address-cells = <2>;
117 #size-cells = <2>;
119 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
147 compatible = "simple-bus";
148 #address-cells = <2>;
149 #size-cells = <2>;
167 thermal_zones: thermal-zones {
168 #include "k3-j721s2-thermal.dtsi"
172 /* Now include peripherals from each bus segment */
173 #include "k3-j721s2-main.dtsi"
174 #include "k3-j721s2-mcu-wakeup.dtsi"