Lines Matching +full:j721e +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
24 bootph-all;
27 k3_clks: clock-controller {
28 compatible = "ti,k2g-sci-clk";
29 #clock-cells = <2>;
30 bootph-all;
33 k3_reset: reset-controller {
34 compatible = "ti,sci-reset";
35 #reset-cells = <2>;
36 bootph-all;
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
47 compatible = "ti,am654-chipid";
49 bootph-all;
54 compatible = "ti,am654-secure-proxy";
55 #mbox-cells = <1>;
56 reg-names = "target_data", "rt", "scfg";
60 bootph-pre-ram;
65 * firmware on non-MPU processors
71 compatible = "mmio-sram";
74 #address-cells = <1>;
75 #size-cells = <1>;
79 compatible = "pinctrl-single";
82 #pinctrl-cells = <1>;
83 pinctrl-single,register-width = <32>;
84 pinctrl-single,function-mask = <0xffffffff>;
88 compatible = "pinctrl-single";
91 #pinctrl-cells = <1>;
92 pinctrl-single,register-width = <32>;
93 pinctrl-single,function-mask = <0xffffffff>;
97 compatible = "pinctrl-single";
100 #pinctrl-cells = <1>;
101 pinctrl-single,register-width = <32>;
102 pinctrl-single,function-mask = <0xffffffff>;
106 compatible = "pinctrl-single";
109 #pinctrl-cells = <1>;
110 pinctrl-single,register-width = <32>;
111 pinctrl-single,function-mask = <0xffffffff>;
116 compatible = "pinctrl-single";
118 #pinctrl-cells = <1>;
119 pinctrl-single,register-width = <32>;
120 pinctrl-single,function-mask = <0x0000000f>;
121 /* Non-MPU Firmware usage */
127 compatible = "pinctrl-single";
129 #pinctrl-cells = <1>;
130 pinctrl-single,register-width = <32>;
131 pinctrl-single,function-mask = <0x0000000f>;
132 /* Non-MPU Firmware usage */
136 wkup_gpio_intr: interrupt-controller@42200000 {
137 compatible = "ti,sci-intr";
139 ti,intr-trigger-type = <1>;
140 interrupt-controller;
141 interrupt-parent = <&gic500>;
142 #interrupt-cells = <1>;
144 ti,sci-dev-id = <125>;
145 ti,interrupt-ranges = <16 960 16>;
149 compatible = "simple-bus";
150 #address-cells = <1>;
151 #size-cells = <1>;
154 cpsw_mac_syscon: ethernet-mac-syscon@200 {
155 compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
160 compatible = "ti,am654-phy-gmii-sel";
162 #phy-cells = <1>;
168 compatible = "ti,am654-timer";
172 clock-names = "fck";
173 assigned-clocks = <&k3_clks 35 1>;
174 assigned-clock-parents = <&k3_clks 35 2>;
175 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
176 bootph-pre-ram;
177 ti,timer-pwm;
178 /* Non-MPU Firmware usage */
183 compatible = "ti,am654-timer";
187 clock-names = "fck";
188 assigned-clocks = <&k3_clks 83 1>;
189 assigned-clock-parents = <&k3_clks 83 2>;
190 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
191 ti,timer-pwm;
192 /* Non-MPU Firmware usage */
197 compatible = "ti,am654-timer";
201 clock-names = "fck";
202 assigned-clocks = <&k3_clks 84 1>;
203 assigned-clock-parents = <&k3_clks 84 2>;
204 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
205 ti,timer-pwm;
206 /* Non-MPU Firmware usage */
211 compatible = "ti,am654-timer";
215 clock-names = "fck";
216 assigned-clocks = <&k3_clks 85 1>;
217 assigned-clock-parents = <&k3_clks 85 2>;
218 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
219 ti,timer-pwm;
220 /* Non-MPU Firmware usage */
225 compatible = "ti,am654-timer";
229 clock-names = "fck";
230 assigned-clocks = <&k3_clks 86 1>;
231 assigned-clock-parents = <&k3_clks 86 2>;
232 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
233 ti,timer-pwm;
234 /* Non-MPU Firmware usage */
239 compatible = "ti,am654-timer";
243 clock-names = "fck";
244 assigned-clocks = <&k3_clks 87 1>;
245 assigned-clock-parents = <&k3_clks 87 2>;
246 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
247 ti,timer-pwm;
248 /* Non-MPU Firmware usage */
253 compatible = "ti,am654-timer";
257 clock-names = "fck";
258 assigned-clocks = <&k3_clks 88 1>;
259 assigned-clock-parents = <&k3_clks 88 2>;
260 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
261 ti,timer-pwm;
262 /* Non-MPU Firmware usage */
267 compatible = "ti,am654-timer";
271 clock-names = "fck";
272 assigned-clocks = <&k3_clks 89 1>;
273 assigned-clock-parents = <&k3_clks 89 2>;
274 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
275 ti,timer-pwm;
276 /* Non-MPU Firmware usage */
281 compatible = "ti,am654-timer";
285 clock-names = "fck";
286 assigned-clocks = <&k3_clks 90 1>;
287 assigned-clock-parents = <&k3_clks 90 2>;
288 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
289 ti,timer-pwm;
290 /* Non-MPU Firmware usage */
295 compatible = "ti,am654-timer";
299 clock-names = "fck";
300 assigned-clocks = <&k3_clks 91 1>;
301 assigned-clock-parents = <&k3_clks 91 2>;
302 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
303 ti,timer-pwm;
304 /* Non-MPU Firmware usage */
309 compatible = "ti,j721e-uart", "ti,am654-uart";
313 clock-names = "fclk";
314 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
319 compatible = "ti,j721e-uart", "ti,am654-uart";
323 clock-names = "fclk";
324 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
329 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
331 gpio-controller;
332 #gpio-cells = <2>;
333 interrupt-parent = <&wkup_gpio_intr>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
338 ti,davinci-gpio-unbanked = <0>;
339 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
341 clock-names = "gpio";
346 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
348 gpio-controller;
349 #gpio-cells = <2>;
350 interrupt-parent = <&wkup_gpio_intr>;
352 interrupt-controller;
353 #interrupt-cells = <2>;
355 ti,davinci-gpio-unbanked = <0>;
356 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
358 clock-names = "gpio";
362 wkup_i2c0: i2c@42120000 {
363 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
366 #address-cells = <1>;
367 #size-cells = <0>;
369 clock-names = "fck";
370 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
371 bootph-all;
375 mcu_i2c0: i2c@40b00000 {
376 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
379 #address-cells = <1>;
380 #size-cells = <0>;
382 clock-names = "fck";
383 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
387 mcu_i2c1: i2c@40b10000 {
388 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
391 #address-cells = <1>;
392 #size-cells = <0>;
394 clock-names = "fck";
395 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
403 reg-names = "m_can", "message_ram";
404 power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
406 clock-names = "hclk", "cclk";
409 interrupt-names = "int0", "int1";
410 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
418 reg-names = "m_can", "message_ram";
419 power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
421 clock-names = "hclk", "cclk";
424 interrupt-names = "int0", "int1";
425 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
430 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
433 #address-cells = <1>;
434 #size-cells = <0>;
435 power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>;
441 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
444 #address-cells = <1>;
445 #size-cells = <0>;
446 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
452 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
463 compatible = "simple-bus";
464 #address-cells = <2>;
465 #size-cells = <2>;
467 dma-coherent;
468 dma-ranges;
470 ti,sci-dev-id = <267>;
473 compatible = "ti,am654-navss-ringacc";
479 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
480 bootph-all;
481 ti,num-rings = <286>;
482 ti,sci-rm-range-gp-rings = <0x1>;
484 ti,sci-dev-id = <272>;
485 msi-parent = <&main_udmass_inta>;
488 mcu_udmap: dma-controller@285c0000 {
489 compatible = "ti,j721e-navss-mcu-udmap";
496 reg-names = "gcfg", "rchanrt", "tchanrt",
498 msi-parent = <&main_udmass_inta>;
499 #dma-cells = <1>;
500 bootph-all;
503 ti,sci-dev-id = <273>;
505 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
507 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
509 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
514 compatible = "ti,am654-secure-proxy";
515 #mbox-cells = <1>;
516 reg-names = "target_data", "rt", "scfg";
520 bootph-pre-ram;
525 * firmware on non-MPU processors
531 compatible = "ti,j721e-cpsw-nuss";
532 #address-cells = <2>;
533 #size-cells = <2>;
535 reg-names = "cpsw_nuss";
537 dma-coherent;
539 clock-names = "fck";
540 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
551 dma-names = "tx0", "tx1", "tx2", "tx3",
555 ethernet-ports {
556 #address-cells = <1>;
557 #size-cells = <0>;
561 ti,mac-only;
563 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
569 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
571 #address-cells = <1>;
572 #size-cells = <0>;
574 clock-names = "fck";
579 compatible = "ti,am65-cpts";
582 clock-names = "cpts";
583 assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */
584 assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */
585 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
586 interrupt-names = "cpts";
587 ti,cpts-ext-ts-inputs = <4>;
588 ti,cpts-periodic-outputs = <2>;
593 compatible = "ti,am3359-tscadc";
596 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
598 assigned-clocks = <&k3_clks 0 2>;
599 assigned-clock-rates = <60000000>;
600 clock-names = "fck";
603 dma-names = "fifo0", "fifo1";
607 #io-channel-cells = <1>;
608 compatible = "ti,am3359-adc";
613 compatible = "ti,am3359-tscadc";
616 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
618 assigned-clocks = <&k3_clks 1 2>;
619 assigned-clock-rates = <60000000>;
620 clock-names = "fck";
623 dma-names = "fifo0", "fifo1";
627 #io-channel-cells = <1>;
628 compatible = "ti,am3359-adc";
633 compatible = "simple-bus";
634 #address-cells = <2>;
635 #size-cells = <2>;
641 compatible = "ti,am654-ospi", "cdns,qspi-nor";
645 cdns,fifo-depth = <256>;
646 cdns,fifo-width = <4>;
647 cdns,trigger-address = <0x0>;
649 assigned-clocks = <&k3_clks 109 5>;
650 assigned-clock-parents = <&k3_clks 109 7>;
651 assigned-clock-rates = <166666666>;
652 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
653 #address-cells = <1>;
654 #size-cells = <0>;
660 compatible = "ti,am654-ospi", "cdns,qspi-nor";
664 cdns,fifo-depth = <256>;
665 cdns,fifo-width = <4>;
666 cdns,trigger-address = <0x0>;
668 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
669 #address-cells = <1>;
670 #size-cells = <0>;
676 wkup_vtm0: temperature-sensor@42040000 {
677 compatible = "ti,j7200-vtm";
680 power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>;
681 #thermal-sensor-cells = <1>;
682 bootph-pre-ram;
686 compatible = "ti,j721s2-r5fss";
687 ti,cluster-mode = <1>;
688 #address-cells = <1>;
689 #size-cells = <1>;
692 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
695 compatible = "ti,j721s2-r5f";
698 reg-names = "atcm", "btcm";
700 ti,sci-dev-id = <284>;
701 ti,sci-proc-ids = <0x01 0xff>;
703 firmware-name = "j721s2-mcu-r5f0_0-fw";
704 ti,atcm-enable = <1>;
705 ti,btcm-enable = <1>;
710 compatible = "ti,j721s2-r5f";
713 reg-names = "atcm", "btcm";
715 ti,sci-dev-id = <285>;
716 ti,sci-proc-ids = <0x02 0xff>;
718 firmware-name = "j721s2-mcu-r5f0_1-fw";
719 ti,atcm-enable = <1>;
720 ti,btcm-enable = <1>;
726 compatible = "ti,j721e-esm";
728 ti,esm-pins = <95>;
729 bootph-pre-ram;
733 compatible = "ti,j721e-esm";
735 ti,esm-pins = <63>;
736 bootph-pre-ram;
744 compatible = "ti,j7-rti-wdt";
747 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
748 assigned-clocks = <&k3_clks 295 1>;
749 assigned-clock-parents = <&k3_clks 295 5>;
755 compatible = "ti,j7-rti-wdt";
758 power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
759 assigned-clocks = <&k3_clks 296 1>;
760 assigned-clock-parents = <&k3_clks 296 5>;