Lines Matching +full:am654 +full:- +full:vtm
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
26 k3_clks: clock-controller {
27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
33 #reset-cells = <2>;
38 compatible = "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
44 compatible = "ti,am654-chipid";
50 compatible = "ti,am654-secure-proxy";
51 #mbox-cells = <1>;
52 reg-names = "target_data", "rt", "scfg";
59 * firmware on non-MPU processors
65 compatible = "mmio-sram";
68 #address-cells = <1>;
69 #size-cells = <1>;
73 compatible = "pinctrl-single";
76 #pinctrl-cells = <1>;
77 pinctrl-single,register-width = <32>;
78 pinctrl-single,function-mask = <0xffffffff>;
82 compatible = "pinctrl-single";
85 #pinctrl-cells = <1>;
86 pinctrl-single,register-width = <32>;
87 pinctrl-single,function-mask = <0xffffffff>;
91 compatible = "pinctrl-single";
94 #pinctrl-cells = <1>;
95 pinctrl-single,register-width = <32>;
96 pinctrl-single,function-mask = <0xffffffff>;
100 compatible = "pinctrl-single";
103 #pinctrl-cells = <1>;
104 pinctrl-single,register-width = <32>;
105 pinctrl-single,function-mask = <0xffffffff>;
110 compatible = "pinctrl-single";
112 #pinctrl-cells = <1>;
113 pinctrl-single,register-width = <32>;
114 pinctrl-single,function-mask = <0x0000000f>;
115 /* Non-MPU Firmware usage */
121 compatible = "pinctrl-single";
123 #pinctrl-cells = <1>;
124 pinctrl-single,register-width = <32>;
125 pinctrl-single,function-mask = <0x0000000f>;
126 /* Non-MPU Firmware usage */
130 wkup_gpio_intr: interrupt-controller@42200000 {
131 compatible = "ti,sci-intr";
133 ti,intr-trigger-type = <1>;
134 interrupt-controller;
135 interrupt-parent = <&gic500>;
136 #interrupt-cells = <1>;
138 ti,sci-dev-id = <125>;
139 ti,interrupt-ranges = <16 960 16>;
143 compatible = "simple-bus";
144 #address-cells = <1>;
145 #size-cells = <1>;
148 cpsw_mac_syscon: ethernet-mac-syscon@200 {
149 compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
154 compatible = "ti,am654-phy-gmii-sel";
156 #phy-cells = <1>;
162 compatible = "ti,am654-timer";
166 clock-names = "fck";
167 assigned-clocks = <&k3_clks 35 1>;
168 assigned-clock-parents = <&k3_clks 35 2>;
169 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
170 ti,timer-pwm;
171 /* Non-MPU Firmware usage */
176 compatible = "ti,am654-timer";
180 clock-names = "fck";
181 assigned-clocks = <&k3_clks 83 1>;
182 assigned-clock-parents = <&k3_clks 83 2>;
183 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
184 ti,timer-pwm;
185 /* Non-MPU Firmware usage */
190 compatible = "ti,am654-timer";
194 clock-names = "fck";
195 assigned-clocks = <&k3_clks 84 1>;
196 assigned-clock-parents = <&k3_clks 84 2>;
197 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
198 ti,timer-pwm;
199 /* Non-MPU Firmware usage */
204 compatible = "ti,am654-timer";
208 clock-names = "fck";
209 assigned-clocks = <&k3_clks 85 1>;
210 assigned-clock-parents = <&k3_clks 85 2>;
211 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
212 ti,timer-pwm;
213 /* Non-MPU Firmware usage */
218 compatible = "ti,am654-timer";
222 clock-names = "fck";
223 assigned-clocks = <&k3_clks 86 1>;
224 assigned-clock-parents = <&k3_clks 86 2>;
225 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
226 ti,timer-pwm;
227 /* Non-MPU Firmware usage */
232 compatible = "ti,am654-timer";
236 clock-names = "fck";
237 assigned-clocks = <&k3_clks 87 1>;
238 assigned-clock-parents = <&k3_clks 87 2>;
239 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
240 ti,timer-pwm;
241 /* Non-MPU Firmware usage */
246 compatible = "ti,am654-timer";
250 clock-names = "fck";
251 assigned-clocks = <&k3_clks 88 1>;
252 assigned-clock-parents = <&k3_clks 88 2>;
253 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
254 ti,timer-pwm;
255 /* Non-MPU Firmware usage */
260 compatible = "ti,am654-timer";
264 clock-names = "fck";
265 assigned-clocks = <&k3_clks 89 1>;
266 assigned-clock-parents = <&k3_clks 89 2>;
267 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
268 ti,timer-pwm;
269 /* Non-MPU Firmware usage */
274 compatible = "ti,am654-timer";
278 clock-names = "fck";
279 assigned-clocks = <&k3_clks 90 1>;
280 assigned-clock-parents = <&k3_clks 90 2>;
281 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
282 ti,timer-pwm;
283 /* Non-MPU Firmware usage */
288 compatible = "ti,am654-timer";
292 clock-names = "fck";
293 assigned-clocks = <&k3_clks 91 1>;
294 assigned-clock-parents = <&k3_clks 91 2>;
295 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
296 ti,timer-pwm;
297 /* Non-MPU Firmware usage */
302 compatible = "ti,j721e-uart", "ti,am654-uart";
306 clock-names = "fclk";
307 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
312 compatible = "ti,j721e-uart", "ti,am654-uart";
316 clock-names = "fclk";
317 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
322 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
324 gpio-controller;
325 #gpio-cells = <2>;
326 interrupt-parent = <&wkup_gpio_intr>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
331 ti,davinci-gpio-unbanked = <0>;
332 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
334 clock-names = "gpio";
339 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
341 gpio-controller;
342 #gpio-cells = <2>;
343 interrupt-parent = <&wkup_gpio_intr>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
348 ti,davinci-gpio-unbanked = <0>;
349 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
351 clock-names = "gpio";
356 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
359 #address-cells = <1>;
360 #size-cells = <0>;
362 clock-names = "fck";
363 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
368 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
371 #address-cells = <1>;
372 #size-cells = <0>;
374 clock-names = "fck";
375 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
380 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
383 #address-cells = <1>;
384 #size-cells = <0>;
386 clock-names = "fck";
387 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
395 reg-names = "m_can", "message_ram";
396 power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
398 clock-names = "hclk", "cclk";
401 interrupt-names = "int0", "int1";
402 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
410 reg-names = "m_can", "message_ram";
411 power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
413 clock-names = "hclk", "cclk";
416 interrupt-names = "int0", "int1";
417 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
422 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
425 #address-cells = <1>;
426 #size-cells = <0>;
427 power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>;
433 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
436 #address-cells = <1>;
437 #size-cells = <0>;
438 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
444 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
447 #address-cells = <1>;
448 #size-cells = <0>;
449 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
455 compatible = "simple-bus";
456 #address-cells = <2>;
457 #size-cells = <2>;
459 dma-coherent;
460 dma-ranges;
462 ti,sci-dev-id = <267>;
465 compatible = "ti,am654-navss-ringacc";
471 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
472 ti,num-rings = <286>;
473 ti,sci-rm-range-gp-rings = <0x1>;
475 ti,sci-dev-id = <272>;
476 msi-parent = <&main_udmass_inta>;
479 mcu_udmap: dma-controller@285c0000 {
480 compatible = "ti,j721e-navss-mcu-udmap";
487 reg-names = "gcfg", "rchanrt", "tchanrt",
489 msi-parent = <&main_udmass_inta>;
490 #dma-cells = <1>;
493 ti,sci-dev-id = <273>;
495 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
497 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
499 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
504 compatible = "ti,am654-secure-proxy";
505 #mbox-cells = <1>;
506 reg-names = "target_data", "rt", "scfg";
513 * firmware on non-MPU processors
519 compatible = "ti,j721e-cpsw-nuss";
520 #address-cells = <2>;
521 #size-cells = <2>;
523 reg-names = "cpsw_nuss";
525 dma-coherent;
527 clock-names = "fck";
528 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
539 dma-names = "tx0", "tx1", "tx2", "tx3",
543 ethernet-ports {
544 #address-cells = <1>;
545 #size-cells = <0>;
549 ti,mac-only;
551 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
557 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
559 #address-cells = <1>;
560 #size-cells = <0>;
562 clock-names = "fck";
567 compatible = "ti,am65-cpts";
570 clock-names = "cpts";
571 assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */
572 assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */
573 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
574 interrupt-names = "cpts";
575 ti,cpts-ext-ts-inputs = <4>;
576 ti,cpts-periodic-outputs = <2>;
581 compatible = "ti,am3359-tscadc";
584 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
586 assigned-clocks = <&k3_clks 0 2>;
587 assigned-clock-rates = <60000000>;
588 clock-names = "fck";
591 dma-names = "fifo0", "fifo1";
595 #io-channel-cells = <1>;
596 compatible = "ti,am3359-adc";
601 compatible = "ti,am3359-tscadc";
604 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
606 assigned-clocks = <&k3_clks 1 2>;
607 assigned-clock-rates = <60000000>;
608 clock-names = "fck";
611 dma-names = "fifo0", "fifo1";
615 #io-channel-cells = <1>;
616 compatible = "ti,am3359-adc";
621 compatible = "simple-bus";
622 #address-cells = <2>;
623 #size-cells = <2>;
629 compatible = "ti,am654-ospi", "cdns,qspi-nor";
633 cdns,fifo-depth = <256>;
634 cdns,fifo-width = <4>;
635 cdns,trigger-address = <0x0>;
637 assigned-clocks = <&k3_clks 109 5>;
638 assigned-clock-parents = <&k3_clks 109 7>;
639 assigned-clock-rates = <166666666>;
640 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
641 #address-cells = <1>;
642 #size-cells = <0>;
648 compatible = "ti,am654-ospi", "cdns,qspi-nor";
652 cdns,fifo-depth = <256>;
653 cdns,fifo-width = <4>;
654 cdns,trigger-address = <0x0>;
656 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
657 #address-cells = <1>;
658 #size-cells = <0>;
664 wkup_vtm0: temperature-sensor@42040000 {
665 compatible = "ti,j7200-vtm";
668 power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>;
669 #thermal-sensor-cells = <1>;
673 compatible = "ti,j721s2-r5fss";
674 ti,cluster-mode = <1>;
675 #address-cells = <1>;
676 #size-cells = <1>;
679 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
682 compatible = "ti,j721s2-r5f";
685 reg-names = "atcm", "btcm";
687 ti,sci-dev-id = <284>;
688 ti,sci-proc-ids = <0x01 0xff>;
690 firmware-name = "j721s2-mcu-r5f0_0-fw";
691 ti,atcm-enable = <1>;
692 ti,btcm-enable = <1>;
697 compatible = "ti,j721s2-r5f";
700 reg-names = "atcm", "btcm";
702 ti,sci-dev-id = <285>;
703 ti,sci-proc-ids = <0x02 0xff>;
705 firmware-name = "j721s2-mcu-r5f0_1-fw";
706 ti,atcm-enable = <1>;
707 ti,btcm-enable = <1>;
713 compatible = "ti,j721e-esm";
715 ti,esm-pins = <95>;
716 bootph-pre-ram;
720 compatible = "ti,j721e-esm";
722 ti,esm-pins = <63>;
723 bootph-pre-ram;
731 compatible = "ti,j7-rti-wdt";
734 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
735 assigned-clocks = <&k3_clks 295 1>;
736 assigned-clock-parents = <&k3_clks 295 5>;
742 compatible = "ti,j7-rti-wdt";
745 power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
746 assigned-clocks = <&k3_clks 296 1>;
747 assigned-clock-parents = <&k3_clks 296 5>;