Lines Matching +full:0 +full:xf007
19 reg = <0x00 0x44083000 0x00 0x1000>;
41 ranges = <0x0 0x00 0x43000000 0x20000>;
45 reg = <0x14 0x4>;
53 reg = <0x00 0x43600000 0x00 0x10000>,
54 <0x00 0x44880000 0x00 0x20000>,
55 <0x00 0x44860000 0x00 0x20000>;
66 reg = <0x00 0x41c00000 0x00 0x100000>;
67 ranges = <0x00 0x00 0x41c00000 0x100000>;
74 /* Proxy 0 addressing */
75 reg = <0x00 0x4301c000 0x00 0x034>;
78 pinctrl-single,function-mask = <0xffffffff>;
83 /* Proxy 0 addressing */
84 reg = <0x00 0x4301c038 0x00 0x02C>;
87 pinctrl-single,function-mask = <0xffffffff>;
92 /* Proxy 0 addressing */
93 reg = <0x00 0x4301c068 0x00 0x120>;
96 pinctrl-single,function-mask = <0xffffffff>;
101 /* Proxy 0 addressing */
102 reg = <0x00 0x4301c190 0x00 0x004>;
105 pinctrl-single,function-mask = <0xffffffff>;
111 reg = <0x00 0x40f04200 0x00 0x28>;
114 pinctrl-single,function-mask = <0x0000000f>;
122 reg = <0x00 0x40f04280 0x00 0x28>;
125 pinctrl-single,function-mask = <0x0000000f>;
132 reg = <0x00 0x42200000 0x00 0x400>;
146 ranges = <0x0 0x0 0x40f00000 0x20000>;
150 reg = <0x200 0x8>;
155 reg = <0x4040 0x4>;
163 reg = <0x00 0x40400000 0x00 0x400>;
177 reg = <0x00 0x40410000 0x00 0x400>;
191 reg = <0x00 0x40420000 0x00 0x400>;
205 reg = <0x00 0x40430000 0x00 0x400>;
219 reg = <0x00 0x40440000 0x00 0x400>;
233 reg = <0x00 0x40450000 0x00 0x400>;
247 reg = <0x00 0x40460000 0x00 0x400>;
261 reg = <0x00 0x40470000 0x00 0x400>;
275 reg = <0x00 0x40480000 0x00 0x400>;
289 reg = <0x00 0x40490000 0x00 0x400>;
303 reg = <0x00 0x42300000 0x00 0x200>;
313 reg = <0x00 0x40a00000 0x00 0x200>;
323 reg = <0x00 0x42110000 0x00 0x100>;
331 ti,davinci-gpio-unbanked = <0>;
333 clocks = <&k3_clks 115 0>;
340 reg = <0x00 0x42100000 0x00 0x100>;
348 ti,davinci-gpio-unbanked = <0>;
350 clocks = <&k3_clks 116 0>;
357 reg = <0x00 0x42120000 0x00 0x100>;
360 #size-cells = <0>;
369 reg = <0x00 0x40b00000 0x00 0x100>;
372 #size-cells = <0>;
381 reg = <0x00 0x40b10000 0x00 0x100>;
384 #size-cells = <0>;
393 reg = <0x00 0x40528000 0x00 0x200>,
394 <0x00 0x40500000 0x00 0x8000>;
397 clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
402 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
408 reg = <0x00 0x40568000 0x00 0x200>,
409 <0x00 0x40540000 0x00 0x8000>;
412 clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
417 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
423 reg = <0x00 0x040300000 0x00 0x400>;
426 #size-cells = <0>;
428 clocks = <&k3_clks 347 0>;
434 reg = <0x00 0x040310000 0x00 0x400>;
437 #size-cells = <0>;
439 clocks = <&k3_clks 348 0>;
445 reg = <0x00 0x040320000 0x00 0x400>;
448 #size-cells = <0>;
450 clocks = <&k3_clks 349 0>;
458 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
466 reg = <0x0 0x2b800000 0x0 0x400000>,
467 <0x0 0x2b000000 0x0 0x400000>,
468 <0x0 0x28590000 0x0 0x100>,
469 <0x0 0x2a500000 0x0 0x40000>,
470 <0x0 0x28440000 0x0 0x40000>;
473 ti,sci-rm-range-gp-rings = <0x1>;
481 reg = <0x0 0x285c0000 0x0 0x100>,
482 <0x0 0x2a800000 0x0 0x40000>,
483 <0x0 0x2aa00000 0x0 0x40000>,
484 <0x0 0x284a0000 0x0 0x4000>,
485 <0x0 0x284c0000 0x0 0x4000>,
486 <0x0 0x28400000 0x0 0x2000>;
495 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
496 <0x0f>; /* TX_HCHAN */
497 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
498 <0x0b>; /* RX_HCHAN */
499 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
507 reg = <0x00 0x2a480000 0x00 0x80000>,
508 <0x00 0x2a380000 0x00 0x80000>,
509 <0x00 0x2a400000 0x00 0x80000>;
522 reg = <0x0 0x46000000 0x0 0x200000>;
524 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
530 dmas = <&mcu_udmap 0xf000>,
531 <&mcu_udmap 0xf001>,
532 <&mcu_udmap 0xf002>,
533 <&mcu_udmap 0xf003>,
534 <&mcu_udmap 0xf004>,
535 <&mcu_udmap 0xf005>,
536 <&mcu_udmap 0xf006>,
537 <&mcu_udmap 0xf007>,
538 <&mcu_udmap 0x7000>;
545 #size-cells = <0>;
551 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
558 reg = <0x0 0xf00 0x0 0x100>;
560 #size-cells = <0>;
568 reg = <0x0 0x3d000 0x0 0x400>;
582 reg = <0x00 0x40200000 0x00 0x1000>;
584 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
585 clocks = <&k3_clks 0 0>;
586 assigned-clocks = <&k3_clks 0 2>;
589 dmas = <&main_udmap 0x7400>,
590 <&main_udmap 0x7401>;
602 reg = <0x00 0x40210000 0x00 0x1000>;
605 clocks = <&k3_clks 1 0>;
609 dmas = <&main_udmap 0x7402>,
610 <&main_udmap 0x7403>;
624 ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
625 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
626 <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
630 reg = <0x00 0x47040000 0x00 0x100>,
631 <0x05 0x00000000 0x01 0x00000000>;
635 cdns,trigger-address = <0x0>;
642 #size-cells = <0>;
649 reg = <0x00 0x47050000 0x00 0x100>,
650 <0x07 0x00000000 0x01 0x00000000>;
654 cdns,trigger-address = <0x0>;
658 #size-cells = <0>;
666 reg = <0x00 0x42040000 0x0 0x350>,
667 <0x00 0x42050000 0x0 0x350>;
677 ranges = <0x41000000 0x00 0x41000000 0x20000>,
678 <0x41400000 0x00 0x41400000 0x20000>;
683 reg = <0x41000000 0x00010000>,
684 <0x41010000 0x00010000>;
688 ti,sci-proc-ids = <0x01 0xff>;
698 reg = <0x41400000 0x00010000>,
699 <0x41410000 0x00010000>;
703 ti,sci-proc-ids = <0x02 0xff>;
714 reg = <0x00 0x40800000 0x00 0x1000>;
721 reg = <0x00 0x42080000 0x00 0x1000>;
732 reg = <0x00 0x40600000 0x00 0x100>;
743 reg = <0x00 0x40610000 0x00 0x100>;