Lines Matching +full:am654 +full:- +full:serdes +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
24 #size-cells = <1>;
27 atf-sram@0 {
31 tifs-sram@1f0000 {
35 l3cache-sram@200000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
43 #address-cells = <1>;
44 #size-cells = <1>;
47 usb_serdes_mux: mux-controller@0 {
48 compatible = "reg-mux";
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
55 compatible = "ti,am654-phy-gmii-sel";
57 #phy-cells = <1>;
60 serdes_ln_ctrl: mux-controller@80 {
61 compatible = "reg-mux";
63 #mux-control-cells = <1>;
64 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
68 ehrpwm_tbclk: clock-controller@140 {
69 compatible = "ti,am654-ehrpwm-tbclk";
71 #clock-cells = <1>;
76 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
77 #pwm-cells = <3>;
79 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
81 clock-names = "tbclk", "fck";
86 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
87 #pwm-cells = <3>;
89 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
91 clock-names = "tbclk", "fck";
96 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
97 #pwm-cells = <3>;
99 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
101 clock-names = "tbclk", "fck";
106 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
107 #pwm-cells = <3>;
109 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
111 clock-names = "tbclk", "fck";
116 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
117 #pwm-cells = <3>;
119 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
121 clock-names = "tbclk", "fck";
126 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
127 #pwm-cells = <3>;
129 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
131 clock-names = "tbclk", "fck";
135 gic500: interrupt-controller@1800000 {
136 compatible = "arm,gic-v3";
137 #address-cells = <2>;
138 #size-cells = <2>;
140 #interrupt-cells = <3>;
141 interrupt-controller;
151 gic_its: msi-controller@1820000 {
152 compatible = "arm,gic-v3-its";
154 socionext,synquacer-pre-its = <0x1000000 0x400000>;
155 msi-controller;
156 #msi-cells = <1>;
160 main_gpio_intr: interrupt-controller@a00000 {
161 compatible = "ti,sci-intr";
163 ti,intr-trigger-type = <1>;
164 interrupt-controller;
165 interrupt-parent = <&gic500>;
166 #interrupt-cells = <1>;
168 ti,sci-dev-id = <148>;
169 ti,interrupt-ranges = <8 392 56>;
173 compatible = "pinctrl-single";
176 #pinctrl-cells = <1>;
177 pinctrl-single,register-width = <32>;
178 pinctrl-single,function-mask = <0xffffffff>;
183 compatible = "pinctrl-single";
185 #pinctrl-cells = <1>;
186 pinctrl-single,register-width = <32>;
187 pinctrl-single,function-mask = <0x00000007>;
192 compatible = "pinctrl-single";
194 #pinctrl-cells = <1>;
195 pinctrl-single,register-width = <32>;
196 pinctrl-single,function-mask = <0x0000001f>;
200 compatible = "ti,j721e-sa2ul";
202 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
203 #address-cells = <2>;
204 #size-cells = <2>;
209 dma-names = "tx", "rx1", "rx2";
212 compatible = "inside-secure,safexcel-eip76";
219 compatible = "ti,am654-timer";
223 clock-names = "fck";
224 assigned-clocks = <&k3_clks 63 1>;
225 assigned-clock-parents = <&k3_clks 63 2>;
226 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
227 ti,timer-pwm;
231 compatible = "ti,am654-timer";
235 clock-names = "fck";
236 assigned-clocks = <&k3_clks 64 1>;
237 assigned-clock-parents = <&k3_clks 64 2>;
238 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
239 ti,timer-pwm;
243 compatible = "ti,am654-timer";
247 clock-names = "fck";
248 assigned-clocks = <&k3_clks 65 1>;
249 assigned-clock-parents = <&k3_clks 65 2>;
250 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
251 ti,timer-pwm;
255 compatible = "ti,am654-timer";
259 clock-names = "fck";
260 assigned-clocks = <&k3_clks 66 1>;
261 assigned-clock-parents = <&k3_clks 66 2>;
262 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
263 ti,timer-pwm;
267 compatible = "ti,am654-timer";
271 clock-names = "fck";
272 assigned-clocks = <&k3_clks 67 1>;
273 assigned-clock-parents = <&k3_clks 67 2>;
274 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
275 ti,timer-pwm;
279 compatible = "ti,am654-timer";
283 clock-names = "fck";
284 assigned-clocks = <&k3_clks 68 1>;
285 assigned-clock-parents = <&k3_clks 68 2>;
286 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
287 ti,timer-pwm;
291 compatible = "ti,am654-timer";
295 clock-names = "fck";
296 assigned-clocks = <&k3_clks 69 1>;
297 assigned-clock-parents = <&k3_clks 69 2>;
298 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
299 ti,timer-pwm;
303 compatible = "ti,am654-timer";
307 clock-names = "fck";
308 assigned-clocks = <&k3_clks 70 1>;
309 assigned-clock-parents = <&k3_clks 70 2>;
310 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
311 ti,timer-pwm;
315 compatible = "ti,am654-timer";
319 clock-names = "fck";
320 assigned-clocks = <&k3_clks 71 1>;
321 assigned-clock-parents = <&k3_clks 71 2>;
322 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
323 ti,timer-pwm;
327 compatible = "ti,am654-timer";
331 clock-names = "fck";
332 assigned-clocks = <&k3_clks 72 1>;
333 assigned-clock-parents = <&k3_clks 72 2>;
334 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
335 ti,timer-pwm;
339 compatible = "ti,am654-timer";
343 clock-names = "fck";
344 assigned-clocks = <&k3_clks 73 1>;
345 assigned-clock-parents = <&k3_clks 73 2>;
346 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
347 ti,timer-pwm;
351 compatible = "ti,am654-timer";
355 clock-names = "fck";
356 assigned-clocks = <&k3_clks 74 1>;
357 assigned-clock-parents = <&k3_clks 74 2>;
358 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
359 ti,timer-pwm;
363 compatible = "ti,am654-timer";
367 clock-names = "fck";
368 assigned-clocks = <&k3_clks 75 1>;
369 assigned-clock-parents = <&k3_clks 75 2>;
370 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
371 ti,timer-pwm;
375 compatible = "ti,am654-timer";
379 clock-names = "fck";
380 assigned-clocks = <&k3_clks 76 1>;
381 assigned-clock-parents = <&k3_clks 76 2>;
382 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
383 ti,timer-pwm;
387 compatible = "ti,am654-timer";
391 clock-names = "fck";
392 assigned-clocks = <&k3_clks 77 1>;
393 assigned-clock-parents = <&k3_clks 77 2>;
394 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
395 ti,timer-pwm;
399 compatible = "ti,am654-timer";
403 clock-names = "fck";
404 assigned-clocks = <&k3_clks 78 1>;
405 assigned-clock-parents = <&k3_clks 78 2>;
406 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
407 ti,timer-pwm;
411 compatible = "ti,am654-timer";
415 clock-names = "fck";
416 assigned-clocks = <&k3_clks 79 1>;
417 assigned-clock-parents = <&k3_clks 79 2>;
418 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
419 ti,timer-pwm;
423 compatible = "ti,am654-timer";
427 clock-names = "fck";
428 assigned-clocks = <&k3_clks 80 1>;
429 assigned-clock-parents = <&k3_clks 80 2>;
430 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
431 ti,timer-pwm;
435 compatible = "ti,am654-timer";
439 clock-names = "fck";
440 assigned-clocks = <&k3_clks 81 1>;
441 assigned-clock-parents = <&k3_clks 81 2>;
442 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
443 ti,timer-pwm;
447 compatible = "ti,am654-timer";
451 clock-names = "fck";
452 assigned-clocks = <&k3_clks 82 1>;
453 assigned-clock-parents = <&k3_clks 82 2>;
454 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
455 ti,timer-pwm;
459 compatible = "ti,j721e-uart", "ti,am654-uart";
463 clock-names = "fclk";
464 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
469 compatible = "ti,j721e-uart", "ti,am654-uart";
473 clock-names = "fclk";
474 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
479 compatible = "ti,j721e-uart", "ti,am654-uart";
483 clock-names = "fclk";
484 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
489 compatible = "ti,j721e-uart", "ti,am654-uart";
493 clock-names = "fclk";
494 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
499 compatible = "ti,j721e-uart", "ti,am654-uart";
503 clock-names = "fclk";
504 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
509 compatible = "ti,j721e-uart", "ti,am654-uart";
513 clock-names = "fclk";
514 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
519 compatible = "ti,j721e-uart", "ti,am654-uart";
523 clock-names = "fclk";
524 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
529 compatible = "ti,j721e-uart", "ti,am654-uart";
533 clock-names = "fclk";
534 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
539 compatible = "ti,j721e-uart", "ti,am654-uart";
543 clock-names = "fclk";
544 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
549 compatible = "ti,j721e-uart", "ti,am654-uart";
553 clock-names = "fclk";
554 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
559 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
561 gpio-controller;
562 #gpio-cells = <2>;
563 interrupt-parent = <&main_gpio_intr>;
565 interrupt-controller;
566 #interrupt-cells = <2>;
568 ti,davinci-gpio-unbanked = <0>;
569 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
571 clock-names = "gpio";
576 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
578 gpio-controller;
579 #gpio-cells = <2>;
580 interrupt-parent = <&main_gpio_intr>;
582 interrupt-controller;
583 #interrupt-cells = <2>;
585 ti,davinci-gpio-unbanked = <0>;
586 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
588 clock-names = "gpio";
593 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
595 gpio-controller;
596 #gpio-cells = <2>;
597 interrupt-parent = <&main_gpio_intr>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
602 ti,davinci-gpio-unbanked = <0>;
603 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
605 clock-names = "gpio";
610 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
612 gpio-controller;
613 #gpio-cells = <2>;
614 interrupt-parent = <&main_gpio_intr>;
616 interrupt-controller;
617 #interrupt-cells = <2>;
619 ti,davinci-gpio-unbanked = <0>;
620 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
622 clock-names = "gpio";
627 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
630 #address-cells = <1>;
631 #size-cells = <0>;
633 clock-names = "fck";
634 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
638 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
641 #address-cells = <1>;
642 #size-cells = <0>;
644 clock-names = "fck";
645 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
650 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
653 #address-cells = <1>;
654 #size-cells = <0>;
656 clock-names = "fck";
657 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
662 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
665 #address-cells = <1>;
666 #size-cells = <0>;
668 clock-names = "fck";
669 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
674 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
677 #address-cells = <1>;
678 #size-cells = <0>;
680 clock-names = "fck";
681 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
686 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
689 #address-cells = <1>;
690 #size-cells = <0>;
692 clock-names = "fck";
693 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
698 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
701 #address-cells = <1>;
702 #size-cells = <0>;
704 clock-names = "fck";
705 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
709 vpu: video-codec@4210000 {
710 compatible = "ti,j721s2-wave521c", "cnm,wave521c";
714 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
718 compatible = "ti,j721e-sdhci-8bit";
722 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
724 clock-names = "clk_ahb", "clk_xin";
725 assigned-clocks = <&k3_clks 98 1>;
726 assigned-clock-parents = <&k3_clks 98 2>;
727 bus-width = <8>;
728 ti,otap-del-sel-legacy = <0x0>;
729 ti,otap-del-sel-mmc-hs = <0x0>;
730 ti,otap-del-sel-ddr52 = <0x6>;
731 ti,otap-del-sel-hs200 = <0x8>;
732 ti,otap-del-sel-hs400 = <0x5>;
733 ti,itap-del-sel-legacy = <0x10>;
734 ti,itap-del-sel-mmc-hs = <0xa>;
735 ti,strobe-sel = <0x77>;
736 ti,clkbuf-sel = <0x7>;
737 ti,trm-icp = <0x8>;
738 mmc-ddr-1_8v;
739 mmc-hs200-1_8v;
740 mmc-hs400-1_8v;
741 dma-coherent;
746 compatible = "ti,j721e-sdhci-4bit";
750 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
752 clock-names = "clk_ahb", "clk_xin";
753 assigned-clocks = <&k3_clks 99 1>;
754 assigned-clock-parents = <&k3_clks 99 2>;
755 bus-width = <4>;
756 ti,otap-del-sel-legacy = <0x0>;
757 ti,otap-del-sel-sd-hs = <0x0>;
758 ti,otap-del-sel-sdr12 = <0xf>;
759 ti,otap-del-sel-sdr25 = <0xf>;
760 ti,otap-del-sel-sdr50 = <0xc>;
761 ti,otap-del-sel-sdr104 = <0x5>;
762 ti,otap-del-sel-ddr50 = <0xc>;
763 ti,itap-del-sel-legacy = <0x0>;
764 ti,itap-del-sel-sd-hs = <0x0>;
765 ti,itap-del-sel-sdr12 = <0x0>;
766 ti,itap-del-sel-sdr25 = <0x0>;
767 ti,itap-del-sel-ddr50 = <0x2>;
768 ti,clkbuf-sel = <0x7>;
769 ti,trm-icp = <0x8>;
770 dma-coherent;
775 compatible = "simple-bus";
776 #address-cells = <2>;
777 #size-cells = <2>;
779 ti,sci-dev-id = <224>;
780 dma-coherent;
781 dma-ranges;
783 main_navss_intr: interrupt-controller@310e0000 {
784 compatible = "ti,sci-intr";
786 ti,intr-trigger-type = <4>;
787 interrupt-controller;
788 interrupt-parent = <&gic500>;
789 #interrupt-cells = <1>;
791 ti,sci-dev-id = <227>;
792 ti,interrupt-ranges = <0 64 64>,
797 main_udmass_inta: msi-controller@33d00000 {
798 compatible = "ti,sci-inta";
800 interrupt-controller;
801 #interrupt-cells = <0>;
802 interrupt-parent = <&main_navss_intr>;
803 msi-controller;
805 ti,sci-dev-id = <265>;
806 ti,interrupt-ranges = <0 0 256>;
807 ti,unmapped-event-sources = <&main_bcdma_csi>;
811 compatible = "ti,am654-secure-proxy";
812 #mbox-cells = <1>;
813 reg-names = "target_data", "rt", "scfg";
817 interrupt-names = "rx_011";
822 compatible = "ti,am654-hwspinlock";
824 #hwlock-cells = <1>;
828 compatible = "ti,am654-mailbox";
830 #mbox-cells = <1>;
831 ti,mbox-num-users = <4>;
832 ti,mbox-num-fifos = <16>;
833 interrupt-parent = <&main_navss_intr>;
838 compatible = "ti,am654-mailbox";
840 #mbox-cells = <1>;
841 ti,mbox-num-users = <4>;
842 ti,mbox-num-fifos = <16>;
843 interrupt-parent = <&main_navss_intr>;
848 compatible = "ti,am654-mailbox";
850 #mbox-cells = <1>;
851 ti,mbox-num-users = <4>;
852 ti,mbox-num-fifos = <16>;
853 interrupt-parent = <&main_navss_intr>;
858 compatible = "ti,am654-mailbox";
860 #mbox-cells = <1>;
861 ti,mbox-num-users = <4>;
862 ti,mbox-num-fifos = <16>;
863 interrupt-parent = <&main_navss_intr>;
868 compatible = "ti,am654-mailbox";
870 #mbox-cells = <1>;
871 ti,mbox-num-users = <4>;
872 ti,mbox-num-fifos = <16>;
873 interrupt-parent = <&main_navss_intr>;
878 compatible = "ti,am654-mailbox";
880 #mbox-cells = <1>;
881 ti,mbox-num-users = <4>;
882 ti,mbox-num-fifos = <16>;
883 interrupt-parent = <&main_navss_intr>;
888 compatible = "ti,am654-mailbox";
890 #mbox-cells = <1>;
891 ti,mbox-num-users = <4>;
892 ti,mbox-num-fifos = <16>;
893 interrupt-parent = <&main_navss_intr>;
898 compatible = "ti,am654-mailbox";
900 #mbox-cells = <1>;
901 ti,mbox-num-users = <4>;
902 ti,mbox-num-fifos = <16>;
903 interrupt-parent = <&main_navss_intr>;
908 compatible = "ti,am654-mailbox";
910 #mbox-cells = <1>;
911 ti,mbox-num-users = <4>;
912 ti,mbox-num-fifos = <16>;
913 interrupt-parent = <&main_navss_intr>;
918 compatible = "ti,am654-mailbox";
920 #mbox-cells = <1>;
921 ti,mbox-num-users = <4>;
922 ti,mbox-num-fifos = <16>;
923 interrupt-parent = <&main_navss_intr>;
928 compatible = "ti,am654-mailbox";
930 #mbox-cells = <1>;
931 ti,mbox-num-users = <4>;
932 ti,mbox-num-fifos = <16>;
933 interrupt-parent = <&main_navss_intr>;
938 compatible = "ti,am654-mailbox";
940 #mbox-cells = <1>;
941 ti,mbox-num-users = <4>;
942 ti,mbox-num-fifos = <16>;
943 interrupt-parent = <&main_navss_intr>;
948 compatible = "ti,am654-mailbox";
950 #mbox-cells = <1>;
951 ti,mbox-num-users = <4>;
952 ti,mbox-num-fifos = <16>;
953 interrupt-parent = <&main_navss_intr>;
958 compatible = "ti,am654-mailbox";
960 #mbox-cells = <1>;
961 ti,mbox-num-users = <4>;
962 ti,mbox-num-fifos = <16>;
963 interrupt-parent = <&main_navss_intr>;
968 compatible = "ti,am654-mailbox";
970 #mbox-cells = <1>;
971 ti,mbox-num-users = <4>;
972 ti,mbox-num-fifos = <16>;
973 interrupt-parent = <&main_navss_intr>;
978 compatible = "ti,am654-mailbox";
980 #mbox-cells = <1>;
981 ti,mbox-num-users = <4>;
982 ti,mbox-num-fifos = <16>;
983 interrupt-parent = <&main_navss_intr>;
988 compatible = "ti,am654-mailbox";
990 #mbox-cells = <1>;
991 ti,mbox-num-users = <4>;
992 ti,mbox-num-fifos = <16>;
993 interrupt-parent = <&main_navss_intr>;
998 compatible = "ti,am654-mailbox";
1000 #mbox-cells = <1>;
1001 ti,mbox-num-users = <4>;
1002 ti,mbox-num-fifos = <16>;
1003 interrupt-parent = <&main_navss_intr>;
1008 compatible = "ti,am654-mailbox";
1010 #mbox-cells = <1>;
1011 ti,mbox-num-users = <4>;
1012 ti,mbox-num-fifos = <16>;
1013 interrupt-parent = <&main_navss_intr>;
1018 compatible = "ti,am654-mailbox";
1020 #mbox-cells = <1>;
1021 ti,mbox-num-users = <4>;
1022 ti,mbox-num-fifos = <16>;
1023 interrupt-parent = <&main_navss_intr>;
1028 compatible = "ti,am654-mailbox";
1030 #mbox-cells = <1>;
1031 ti,mbox-num-users = <4>;
1032 ti,mbox-num-fifos = <16>;
1033 interrupt-parent = <&main_navss_intr>;
1038 compatible = "ti,am654-mailbox";
1040 #mbox-cells = <1>;
1041 ti,mbox-num-users = <4>;
1042 ti,mbox-num-fifos = <16>;
1043 interrupt-parent = <&main_navss_intr>;
1048 compatible = "ti,am654-mailbox";
1050 #mbox-cells = <1>;
1051 ti,mbox-num-users = <4>;
1052 ti,mbox-num-fifos = <16>;
1053 interrupt-parent = <&main_navss_intr>;
1058 compatible = "ti,am654-mailbox";
1060 #mbox-cells = <1>;
1061 ti,mbox-num-users = <4>;
1062 ti,mbox-num-fifos = <16>;
1063 interrupt-parent = <&main_navss_intr>;
1068 compatible = "ti,am654-navss-ringacc";
1074 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
1075 ti,num-rings = <1024>;
1076 ti,sci-rm-range-gp-rings = <0x1>;
1078 ti,sci-dev-id = <259>;
1079 msi-parent = <&main_udmass_inta>;
1082 main_udmap: dma-controller@31150000 {
1083 compatible = "ti,j721e-navss-main-udmap";
1090 reg-names = "gcfg", "rchanrt", "tchanrt",
1092 msi-parent = <&main_udmass_inta>;
1093 #dma-cells = <1>;
1096 ti,sci-dev-id = <263>;
1099 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1102 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1105 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1108 main_bcdma_csi: dma-controller@311a0000 {
1109 compatible = "ti,j721s2-dmss-bcdma-csi";
1114 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
1115 msi-parent = <&main_udmass_inta>;
1116 #dma-cells = <3>;
1118 ti,sci-dev-id = <225>;
1119 ti,sci-rm-range-rchan = <0x21>;
1120 ti,sci-rm-range-tchan = <0x22>;
1124 compatible = "ti,j721e-cpts";
1126 reg-names = "cpts";
1128 clock-names = "cpts";
1129 assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
1130 assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
1131 interrupts-extended = <&main_navss_intr 391>;
1132 interrupt-names = "cpts";
1133 ti,cpts-periodic-outputs = <6>;
1134 ti,cpts-ext-ts-inputs = <8>;
1139 compatible = "ti,j721e-cpsw-nuss";
1141 reg-names = "cpsw_nuss";
1143 #address-cells = <2>;
1144 #size-cells = <2>;
1145 dma-coherent;
1147 clock-names = "fck";
1148 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
1159 dma-names = "tx0", "tx1", "tx2", "tx3",
1165 ethernet-ports {
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1171 ti,mac-only;
1179 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1181 #address-cells = <1>;
1182 #size-cells = <0>;
1184 clock-names = "fck";
1190 compatible = "ti,am65-cpts";
1193 clock-names = "cpts";
1194 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1195 interrupt-names = "cpts";
1196 ti,cpts-ext-ts-inputs = <4>;
1197 ti,cpts-periodic-outputs = <2>;
1201 usbss0: cdns-usb@4104000 {
1202 compatible = "ti,j721e-usb";
1205 clock-names = "ref", "lpm";
1206 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
1207 assigned-clock-parents = <&k3_clks 360 17>;
1208 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
1209 #address-cells = <2>;
1210 #size-cells = <2>;
1212 dma-coherent;
1221 reg-names = "otg", "xhci", "dev";
1225 interrupt-names = "host", "peripheral", "otg";
1226 maximum-speed = "super-speed";
1232 compatible = "ti,j721e-csi2rx-shim";
1235 #address-cells = <2>;
1236 #size-cells = <2>;
1238 dma-names = "rx0";
1239 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
1242 cdns_csi2rx0: csi-bridge@4504000 {
1243 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1247 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1250 phy-names = "dphy";
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1285 compatible = "ti,j721e-csi2rx-shim";
1288 #address-cells = <2>;
1289 #size-cells = <2>;
1291 dma-names = "rx0";
1292 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
1295 cdns_csi2rx1: csi-bridge@4514000 {
1296 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1300 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1303 phy-names = "dphy";
1306 #address-cells = <1>;
1307 #size-cells = <0>;
1338 compatible = "cdns,dphy-rx";
1340 #phy-cells = <0>;
1341 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1346 compatible = "cdns,dphy-rx";
1348 #phy-cells = <0>;
1349 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
1354 compatible = "ti,j721s2-wiz-10g";
1355 #address-cells = <1>;
1356 #size-cells = <1>;
1357 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
1359 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1360 num-lanes = <4>;
1361 #reset-cells = <1>;
1362 #clock-cells = <1>;
1365 assigned-clocks = <&k3_clks 365 3>;
1366 assigned-clock-parents = <&k3_clks 365 7>;
1368 serdes0: serdes@5060000 {
1369 compatible = "ti,j721e-serdes-10g";
1371 reg-names = "torrent_phy";
1373 reset-names = "torrent_reset";
1376 clock-names = "refclk", "phy_en_refclk";
1377 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1380 assigned-clock-parents = <&k3_clks 365 3>,
1383 #address-cells = <1>;
1384 #size-cells = <0>;
1385 #clock-cells = <1>;
1392 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
1397 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1398 interrupt-names = "link_state";
1401 ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
1402 max-link-speed = <3>;
1403 num-lanes = <4>;
1404 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
1406 clock-names = "fck";
1407 #address-cells = <3>;
1408 #size-cells = <2>;
1409 bus-range = <0x0 0xff>;
1410 vendor-id = <0x104c>;
1411 device-id = <0xb013>;
1412 msi-map = <0x0 &gic_its 0x0 0x10000>;
1413 dma-coherent;
1416 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1417 #interrupt-cells = <1>;
1418 interrupt-map-mask = <0 0 0 7>;
1419 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
1424 status = "disabled"; /* Needs gpio and serdes info */
1426 pcie1_intc: interrupt-controller {
1427 interrupt-controller;
1428 #interrupt-cells = <1>;
1429 interrupt-parent = <&gic500>;
1438 reg-names = "m_can", "message_ram";
1439 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1441 clock-names = "hclk", "cclk";
1444 interrupt-names = "int0", "int1";
1445 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1453 reg-names = "m_can", "message_ram";
1454 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1456 clock-names = "hclk", "cclk";
1459 interrupt-names = "int0", "int1";
1460 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1468 reg-names = "m_can", "message_ram";
1469 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1471 clock-names = "hclk", "cclk";
1474 interrupt-names = "int0", "int1";
1475 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1483 reg-names = "m_can", "message_ram";
1484 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1486 clock-names = "hclk", "cclk";
1489 interrupt-names = "int0", "int1";
1490 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1498 reg-names = "m_can", "message_ram";
1499 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
1501 clock-names = "hclk", "cclk";
1504 interrupt-names = "int0", "int1";
1505 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1513 reg-names = "m_can", "message_ram";
1514 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
1516 clock-names = "hclk", "cclk";
1519 interrupt-names = "int0", "int1";
1520 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1528 reg-names = "m_can", "message_ram";
1529 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1531 clock-names = "hclk", "cclk";
1534 interrupt-names = "int0", "int1";
1535 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1543 reg-names = "m_can", "message_ram";
1544 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1546 clock-names = "hclk", "cclk";
1549 interrupt-names = "int0", "int1";
1550 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1558 reg-names = "m_can", "message_ram";
1559 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1561 clock-names = "hclk", "cclk";
1564 interrupt-names = "int0", "int1";
1565 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1573 reg-names = "m_can", "message_ram";
1574 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1576 clock-names = "hclk", "cclk";
1579 interrupt-names = "int0", "int1";
1580 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1588 reg-names = "m_can", "message_ram";
1589 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1591 clock-names = "hclk", "cclk";
1594 interrupt-names = "int0", "int1";
1595 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1603 reg-names = "m_can", "message_ram";
1604 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1606 clock-names = "hclk", "cclk";
1609 interrupt-names = "int0", "int1";
1610 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1618 reg-names = "m_can", "message_ram";
1619 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
1621 clock-names = "hclk", "cclk";
1624 interrupt-names = "int0", "int1";
1625 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1633 reg-names = "m_can", "message_ram";
1634 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
1636 clock-names = "hclk", "cclk";
1639 interrupt-names = "int0", "int1";
1640 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1648 reg-names = "m_can", "message_ram";
1649 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
1651 clock-names = "hclk", "cclk";
1654 interrupt-names = "int0", "int1";
1655 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1663 reg-names = "m_can", "message_ram";
1664 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
1666 clock-names = "hclk", "cclk";
1669 interrupt-names = "int0", "int1";
1670 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1678 reg-names = "m_can", "message_ram";
1679 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
1681 clock-names = "hclk", "cclk";
1684 interrupt-names = "int0", "int1";
1685 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1693 reg-names = "m_can", "message_ram";
1694 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
1696 clock-names = "hclk", "cclk";
1699 interrupt-names = "int0", "int1";
1700 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1705 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1708 #address-cells = <1>;
1709 #size-cells = <0>;
1710 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
1716 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1719 #address-cells = <1>;
1720 #size-cells = <0>;
1721 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
1727 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1730 #address-cells = <1>;
1731 #size-cells = <0>;
1732 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
1738 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1741 #address-cells = <1>;
1742 #size-cells = <0>;
1743 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
1749 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1752 #address-cells = <1>;
1753 #size-cells = <0>;
1754 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
1760 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1765 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
1771 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1774 #address-cells = <1>;
1775 #size-cells = <0>;
1776 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
1782 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1785 #address-cells = <1>;
1786 #size-cells = <0>;
1787 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
1793 compatible = "ti,j721e-dss";
1811 reg-names = "common_m", "common_s0",
1822 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1823 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
1828 interrupt-names = "common_m",
1839 compatible = "ti,j721s2-r5fss";
1840 ti,cluster-mode = <1>;
1841 #address-cells = <1>;
1842 #size-cells = <1>;
1845 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1848 compatible = "ti,j721s2-r5f";
1851 reg-names = "atcm", "btcm";
1853 ti,sci-dev-id = <279>;
1854 ti,sci-proc-ids = <0x06 0xff>;
1856 firmware-name = "j721s2-main-r5f0_0-fw";
1857 ti,atcm-enable = <1>;
1858 ti,btcm-enable = <1>;
1863 compatible = "ti,j721s2-r5f";
1866 reg-names = "atcm", "btcm";
1868 ti,sci-dev-id = <280>;
1869 ti,sci-proc-ids = <0x07 0xff>;
1871 firmware-name = "j721s2-main-r5f0_1-fw";
1872 ti,atcm-enable = <1>;
1873 ti,btcm-enable = <1>;
1879 compatible = "ti,j721s2-r5fss";
1880 ti,cluster-mode = <1>;
1881 #address-cells = <1>;
1882 #size-cells = <1>;
1885 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1888 compatible = "ti,j721s2-r5f";
1891 reg-names = "atcm", "btcm";
1893 ti,sci-dev-id = <281>;
1894 ti,sci-proc-ids = <0x08 0xff>;
1896 firmware-name = "j721s2-main-r5f1_0-fw";
1897 ti,atcm-enable = <1>;
1898 ti,btcm-enable = <1>;
1903 compatible = "ti,j721s2-r5f";
1906 reg-names = "atcm", "btcm";
1908 ti,sci-dev-id = <282>;
1909 ti,sci-proc-ids = <0x09 0xff>;
1911 firmware-name = "j721s2-main-r5f1_1-fw";
1912 ti,atcm-enable = <1>;
1913 ti,btcm-enable = <1>;
1919 compatible = "ti,j721s2-c71-dsp";
1922 reg-names = "l2sram", "l1dram";
1924 ti,sci-dev-id = <8>;
1925 ti,sci-proc-ids = <0x30 0xff>;
1927 firmware-name = "j721s2-c71_0-fw";
1932 compatible = "ti,j721s2-c71-dsp";
1935 reg-names = "l2sram", "l1dram";
1937 ti,sci-dev-id = <11>;
1938 ti,sci-proc-ids = <0x31 0xff>;
1940 firmware-name = "j721s2-c71_1-fw";
1945 compatible = "ti,j721e-esm";
1947 ti,esm-pins = <688>, <689>;
1948 bootph-pre-ram;
1952 compatible = "ti,j7-rti-wdt";
1955 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1956 assigned-clocks = <&k3_clks 286 1>;
1957 assigned-clock-parents = <&k3_clks 286 5>;
1961 compatible = "ti,j7-rti-wdt";
1964 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
1965 assigned-clocks = <&k3_clks 287 1>;
1966 assigned-clock-parents = <&k3_clks 287 5>;
1975 compatible = "ti,j7-rti-wdt";
1978 power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
1979 assigned-clocks = <&k3_clks 290 1>;
1980 assigned-clock-parents = <&k3_clks 290 5>;
1986 compatible = "ti,j7-rti-wdt";
1989 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1990 assigned-clocks = <&k3_clks 288 1>;
1991 assigned-clock-parents = <&k3_clks 288 5>;
1997 compatible = "ti,j7-rti-wdt";
2000 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
2001 assigned-clocks = <&k3_clks 289 1>;
2002 assigned-clock-parents = <&k3_clks 289 5>;
2008 compatible = "ti,j7-rti-wdt";
2011 power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
2012 assigned-clocks = <&k3_clks 291 1>;
2013 assigned-clock-parents = <&k3_clks 291 5>;
2019 compatible = "ti,j7-rti-wdt";
2022 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
2023 assigned-clocks = <&k3_clks 292 1>;
2024 assigned-clock-parents = <&k3_clks 292 5>;
2030 compatible = "ti,j7-rti-wdt";
2033 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
2034 assigned-clocks = <&k3_clks 293 1>;
2035 assigned-clock-parents = <&k3_clks 293 5>;
2041 compatible = "ti,j7-rti-wdt";
2044 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
2045 assigned-clocks = <&k3_clks 294 1>;
2046 assigned-clock-parents = <&k3_clks 294 5>;