Lines Matching +full:0 +full:x0c400000
13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x0 0x70000000 0x0 0x400000>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
32 reg = <0x1f0000 0x10000>;
36 reg = <0x200000 0x200000>;
42 reg = <0x00 0x00104000 0x00 0x18000>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
47 usb_serdes_mux: mux-controller@0 {
49 reg = <0x0 0x4>;
51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
56 reg = <0x34 0x4>;
62 reg = <0x80 0x10>;
64 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
65 <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
70 reg = <0x140 0x18>;
78 reg = <0x00 0x3000000 0x00 0x100>;
80 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
88 reg = <0x00 0x3010000 0x00 0x100>;
90 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
98 reg = <0x00 0x3020000 0x00 0x100>;
100 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
108 reg = <0x00 0x3030000 0x00 0x100>;
110 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
118 reg = <0x00 0x3040000 0x00 0x100>;
120 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
128 reg = <0x00 0x3050000 0x00 0x100>;
130 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
142 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
143 <0x00 0x01900000 0x00 0x100000>, /* GICR */
144 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
145 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
146 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
153 reg = <0x00 0x01820000 0x00 0x10000>;
154 socionext,synquacer-pre-its = <0x1000000 0x400000>;
162 reg = <0x00 0x00a00000 0x00 0x800>;
174 /* Proxy 0 addressing */
175 reg = <0x0 0x11c000 0x0 0x120>;
178 pinctrl-single,function-mask = <0xffffffff>;
184 reg = <0x00 0x104200 0x00 0x50>;
187 pinctrl-single,function-mask = <0x00000007>;
193 reg = <0x00 0x104280 0x00 0x20>;
196 pinctrl-single,function-mask = <0x0000001f>;
201 reg = <0x00 0x04e00000 0x00 0x1200>;
205 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
207 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
208 <&main_udmap 0x4a41>;
213 reg = <0x00 0x04e10000 0x00 0x7d>;
220 reg = <0x00 0x2400000 0x00 0x400>;
232 reg = <0x00 0x2410000 0x00 0x400>;
244 reg = <0x00 0x2420000 0x00 0x400>;
256 reg = <0x00 0x2430000 0x00 0x400>;
268 reg = <0x00 0x2440000 0x00 0x400>;
280 reg = <0x00 0x2450000 0x00 0x400>;
292 reg = <0x00 0x2460000 0x00 0x400>;
304 reg = <0x00 0x2470000 0x00 0x400>;
316 reg = <0x00 0x2480000 0x00 0x400>;
328 reg = <0x00 0x2490000 0x00 0x400>;
340 reg = <0x00 0x24a0000 0x00 0x400>;
352 reg = <0x00 0x24b0000 0x00 0x400>;
364 reg = <0x00 0x24c0000 0x00 0x400>;
376 reg = <0x00 0x24d0000 0x00 0x400>;
388 reg = <0x00 0x24e0000 0x00 0x400>;
400 reg = <0x00 0x24f0000 0x00 0x400>;
412 reg = <0x00 0x2500000 0x00 0x400>;
424 reg = <0x00 0x2510000 0x00 0x400>;
436 reg = <0x00 0x2520000 0x00 0x400>;
448 reg = <0x00 0x2530000 0x00 0x400>;
460 reg = <0x00 0x02800000 0x00 0x200>;
470 reg = <0x00 0x02810000 0x00 0x200>;
480 reg = <0x00 0x02820000 0x00 0x200>;
490 reg = <0x00 0x02830000 0x00 0x200>;
500 reg = <0x00 0x02840000 0x00 0x200>;
510 reg = <0x00 0x02850000 0x00 0x200>;
520 reg = <0x00 0x02860000 0x00 0x200>;
530 reg = <0x00 0x02870000 0x00 0x200>;
540 reg = <0x00 0x02880000 0x00 0x200>;
550 reg = <0x00 0x02890000 0x00 0x200>;
560 reg = <0x00 0x00600000 0x00 0x100>;
568 ti,davinci-gpio-unbanked = <0>;
570 clocks = <&k3_clks 111 0>;
577 reg = <0x00 0x00610000 0x00 0x100>;
585 ti,davinci-gpio-unbanked = <0>;
587 clocks = <&k3_clks 112 0>;
594 reg = <0x00 0x00620000 0x00 0x100>;
602 ti,davinci-gpio-unbanked = <0>;
604 clocks = <&k3_clks 113 0>;
611 reg = <0x00 0x00630000 0x00 0x100>;
619 ti,davinci-gpio-unbanked = <0>;
621 clocks = <&k3_clks 114 0>;
628 reg = <0x00 0x02000000 0x00 0x100>;
631 #size-cells = <0>;
639 reg = <0x00 0x02010000 0x00 0x100>;
642 #size-cells = <0>;
651 reg = <0x00 0x02020000 0x00 0x100>;
654 #size-cells = <0>;
663 reg = <0x00 0x02030000 0x00 0x100>;
666 #size-cells = <0>;
675 reg = <0x00 0x02040000 0x00 0x100>;
678 #size-cells = <0>;
687 reg = <0x00 0x02050000 0x00 0x100>;
690 #size-cells = <0>;
699 reg = <0x00 0x02060000 0x00 0x100>;
702 #size-cells = <0>;
711 reg = <0x00 0x4210000 0x00 0x10000>;
719 reg = <0x00 0x04f80000 0x00 0x1000>,
720 <0x00 0x04f88000 0x00 0x400>;
728 ti,otap-del-sel-legacy = <0x0>;
729 ti,otap-del-sel-mmc-hs = <0x0>;
730 ti,otap-del-sel-ddr52 = <0x6>;
731 ti,otap-del-sel-hs200 = <0x8>;
732 ti,otap-del-sel-hs400 = <0x5>;
733 ti,itap-del-sel-legacy = <0x10>;
734 ti,itap-del-sel-mmc-hs = <0xa>;
735 ti,strobe-sel = <0x77>;
736 ti,clkbuf-sel = <0x7>;
737 ti,trm-icp = <0x8>;
747 reg = <0x00 0x04fb0000 0x00 0x1000>,
748 <0x00 0x04fb8000 0x00 0x400>;
756 ti,otap-del-sel-legacy = <0x0>;
757 ti,otap-del-sel-sd-hs = <0x0>;
758 ti,otap-del-sel-sdr12 = <0xf>;
759 ti,otap-del-sel-sdr25 = <0xf>;
760 ti,otap-del-sel-sdr50 = <0xc>;
761 ti,otap-del-sel-sdr104 = <0x5>;
762 ti,otap-del-sel-ddr50 = <0xc>;
763 ti,itap-del-sel-legacy = <0x0>;
764 ti,itap-del-sel-sd-hs = <0x0>;
765 ti,itap-del-sel-sdr12 = <0x0>;
766 ti,itap-del-sel-sdr25 = <0x0>;
767 ti,itap-del-sel-ddr50 = <0x2>;
768 ti,clkbuf-sel = <0x7>;
769 ti,trm-icp = <0x8>;
778 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
785 reg = <0x00 0x310e0000 0x00 0x4000>;
792 ti,interrupt-ranges = <0 64 64>,
799 reg = <0x00 0x33d00000 0x00 0x100000>;
801 #interrupt-cells = <0>;
806 ti,interrupt-ranges = <0 0 256>;
814 reg = <0x00 0x32c00000 0x00 0x100000>,
815 <0x00 0x32400000 0x00 0x100000>,
816 <0x00 0x32800000 0x00 0x100000>;
823 reg = <0x00 0x30e00000 0x00 0x1000>;
829 reg = <0x00 0x31f80000 0x00 0x200>;
839 reg = <0x00 0x31f81000 0x00 0x200>;
849 reg = <0x00 0x31f82000 0x00 0x200>;
859 reg = <0x00 0x31f83000 0x00 0x200>;
869 reg = <0x00 0x31f84000 0x00 0x200>;
879 reg = <0x00 0x31f85000 0x00 0x200>;
889 reg = <0x00 0x31f86000 0x00 0x200>;
899 reg = <0x00 0x31f87000 0x00 0x200>;
909 reg = <0x00 0x31f88000 0x00 0x200>;
919 reg = <0x00 0x31f89000 0x00 0x200>;
929 reg = <0x00 0x31f8a000 0x00 0x200>;
939 reg = <0x00 0x31f8b000 0x00 0x200>;
949 reg = <0x00 0x31f90000 0x00 0x200>;
959 reg = <0x00 0x31f91000 0x00 0x200>;
969 reg = <0x00 0x31f92000 0x00 0x200>;
979 reg = <0x00 0x31f93000 0x00 0x200>;
989 reg = <0x00 0x31f94000 0x00 0x200>;
999 reg = <0x00 0x31f95000 0x00 0x200>;
1009 reg = <0x00 0x31f96000 0x00 0x200>;
1019 reg = <0x00 0x31f97000 0x00 0x200>;
1029 reg = <0x00 0x31f98000 0x00 0x200>;
1039 reg = <0x00 0x31f99000 0x00 0x200>;
1049 reg = <0x00 0x31f9a000 0x00 0x200>;
1059 reg = <0x00 0x31f9b000 0x00 0x200>;
1069 reg = <0x0 0x3c000000 0x0 0x400000>,
1070 <0x0 0x38000000 0x0 0x400000>,
1071 <0x0 0x31120000 0x0 0x100>,
1072 <0x0 0x33000000 0x0 0x40000>,
1073 <0x0 0x31080000 0x0 0x40000>;
1076 ti,sci-rm-range-gp-rings = <0x1>;
1084 reg = <0x0 0x31150000 0x0 0x100>,
1085 <0x0 0x34000000 0x0 0x80000>,
1086 <0x0 0x35000000 0x0 0x200000>,
1087 <0x0 0x30b00000 0x0 0x20000>,
1088 <0x0 0x30c00000 0x0 0x8000>,
1089 <0x0 0x30d00000 0x0 0x4000>;
1099 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1100 <0x0f>, /* TX_HCHAN */
1101 <0x10>; /* TX_UHCHAN */
1102 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1103 <0x0b>, /* RX_HCHAN */
1104 <0x0c>; /* RX_UHCHAN */
1105 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1110 reg = <0x00 0x311a0000 0x00 0x100>,
1111 <0x00 0x35d00000 0x00 0x20000>,
1112 <0x00 0x35c00000 0x00 0x10000>,
1113 <0x00 0x35e00000 0x00 0x80000>;
1119 ti,sci-rm-range-rchan = <0x21>;
1120 ti,sci-rm-range-tchan = <0x22>;
1125 reg = <0x0 0x310d0000 0x0 0x400>;
1140 reg = <0x00 0xc200000 0x00 0x200000>;
1142 ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
1150 dmas = <&main_udmap 0xc640>,
1151 <&main_udmap 0xc641>,
1152 <&main_udmap 0xc642>,
1153 <&main_udmap 0xc643>,
1154 <&main_udmap 0xc644>,
1155 <&main_udmap 0xc645>,
1156 <&main_udmap 0xc646>,
1157 <&main_udmap 0xc647>,
1158 <&main_udmap 0x4640>;
1167 #size-cells = <0>;
1180 reg = <0x00 0xf00 0x00 0x100>;
1182 #size-cells = <0>;
1191 reg = <0x00 0x3d000 0x00 0x400>;
1203 reg = <0x00 0x04104000 0x00 0x100>;
1218 reg = <0x00 0x06000000 0x00 0x10000>,
1219 <0x00 0x06010000 0x00 0x10000>,
1220 <0x00 0x06020000 0x00 0x10000>;
1233 reg = <0x00 0x04500000 0x00 0x1000>;
1237 dmas = <&main_bcdma_csi 0 0x4940 0>;
1244 reg = <0x00 0x04504000 0x00 0x1000>;
1254 #size-cells = <0>;
1256 csi0_port0: port@0 {
1257 reg = <0>;
1286 reg = <0x00 0x04510000 0x00 0x1000>;
1290 dmas = <&main_bcdma_csi 0 0x4960 0>;
1297 reg = <0x00 0x04514000 0x00 0x1000>;
1307 #size-cells = <0>;
1309 csi1_port0: port@0 {
1310 reg = <0>;
1339 reg = <0x00 0x04580000 0x00 0x1100>;
1340 #phy-cells = <0>;
1347 reg = <0x00 0x04590000 0x00 0x1100>;
1348 #phy-cells = <0>;
1358 clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
1363 ranges = <0x5060000 0x0 0x5060000 0x10000>;
1370 reg = <0x05060000 0x00010000>;
1372 resets = <&serdes_wiz0 0>;
1384 #size-cells = <0>;
1393 reg = <0x00 0x02910000 0x00 0x1000>,
1394 <0x00 0x02917000 0x00 0x400>,
1395 <0x00 0x0d800000 0x00 0x800000>,
1396 <0x00 0x18000000 0x00 0x1000>;
1401 ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
1409 bus-range = <0x0 0xff>;
1410 vendor-id = <0x104c>;
1411 device-id = <0xb013>;
1412 msi-map = <0x0 &gic_its 0x0 0x10000>;
1414 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
1415 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
1416 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1418 interrupt-map-mask = <0 0 0 7>;
1419 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
1420 <0 0 0 2 &pcie1_intc 0>, /* INT B */
1421 <0 0 0 3 &pcie1_intc 0>, /* INT C */
1422 <0 0 0 4 &pcie1_intc 0>; /* INT D */
1436 reg = <0x00 0x02701000 0x00 0x200>,
1437 <0x00 0x02708000 0x00 0x8000>;
1440 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
1445 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1451 reg = <0x00 0x02711000 0x00 0x200>,
1452 <0x00 0x02718000 0x00 0x8000>;
1455 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
1460 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1466 reg = <0x00 0x02721000 0x00 0x200>,
1467 <0x00 0x02728000 0x00 0x8000>;
1470 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
1475 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1481 reg = <0x00 0x02731000 0x00 0x200>,
1482 <0x00 0x02738000 0x00 0x8000>;
1485 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
1490 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1496 reg = <0x00 0x02741000 0x00 0x200>,
1497 <0x00 0x02748000 0x00 0x8000>;
1500 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
1505 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1511 reg = <0x00 0x02751000 0x00 0x200>,
1512 <0x00 0x02758000 0x00 0x8000>;
1515 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
1520 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1526 reg = <0x00 0x02761000 0x00 0x200>,
1527 <0x00 0x02768000 0x00 0x8000>;
1530 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
1535 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1541 reg = <0x00 0x02771000 0x00 0x200>,
1542 <0x00 0x02778000 0x00 0x8000>;
1545 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
1550 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1556 reg = <0x00 0x02781000 0x00 0x200>,
1557 <0x00 0x02788000 0x00 0x8000>;
1560 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
1565 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1571 reg = <0x00 0x02791000 0x00 0x200>,
1572 <0x00 0x02798000 0x00 0x8000>;
1575 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
1580 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1586 reg = <0x00 0x027a1000 0x00 0x200>,
1587 <0x00 0x027a8000 0x00 0x8000>;
1590 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
1595 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1601 reg = <0x00 0x027b1000 0x00 0x200>,
1602 <0x00 0x027b8000 0x00 0x8000>;
1605 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
1610 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1616 reg = <0x00 0x027c1000 0x00 0x200>,
1617 <0x00 0x027c8000 0x00 0x8000>;
1620 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
1625 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1631 reg = <0x00 0x027d1000 0x00 0x200>,
1632 <0x00 0x027d8000 0x00 0x8000>;
1635 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
1640 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1646 reg = <0x00 0x02681000 0x00 0x200>,
1647 <0x00 0x02688000 0x00 0x8000>;
1650 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
1655 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1661 reg = <0x00 0x02691000 0x00 0x200>,
1662 <0x00 0x02698000 0x00 0x8000>;
1665 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
1670 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1676 reg = <0x00 0x026a1000 0x00 0x200>,
1677 <0x00 0x026a8000 0x00 0x8000>;
1680 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
1685 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1691 reg = <0x00 0x026b1000 0x00 0x200>,
1692 <0x00 0x026b8000 0x00 0x8000>;
1695 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
1700 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1706 reg = <0x00 0x02100000 0x00 0x400>;
1709 #size-cells = <0>;
1717 reg = <0x00 0x02110000 0x00 0x400>;
1720 #size-cells = <0>;
1728 reg = <0x00 0x02120000 0x00 0x400>;
1731 #size-cells = <0>;
1739 reg = <0x00 0x02130000 0x00 0x400>;
1742 #size-cells = <0>;
1750 reg = <0x00 0x02140000 0x00 0x400>;
1753 #size-cells = <0>;
1761 reg = <0x00 0x02150000 0x00 0x400>;
1764 #size-cells = <0>;
1772 reg = <0x00 0x02160000 0x00 0x400>;
1775 #size-cells = <0>;
1783 reg = <0x00 0x02170000 0x00 0x400>;
1786 #size-cells = <0>;
1794 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1795 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1796 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1797 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1798 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1799 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1800 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1801 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1802 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1803 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1804 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1805 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1806 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1807 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1808 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1809 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1810 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1817 clocks = <&k3_clks 158 0>,
1843 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1844 <0x5d00000 0x00 0x5d00000 0x20000>;
1849 reg = <0x5c00000 0x00010000>,
1850 <0x5c10000 0x00010000>;
1854 ti,sci-proc-ids = <0x06 0xff>;
1864 reg = <0x5d00000 0x00010000>,
1865 <0x5d10000 0x00010000>;
1869 ti,sci-proc-ids = <0x07 0xff>;
1883 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1884 <0x5f00000 0x00 0x5f00000 0x20000>;
1889 reg = <0x5e00000 0x00010000>,
1890 <0x5e10000 0x00010000>;
1894 ti,sci-proc-ids = <0x08 0xff>;
1904 reg = <0x5f00000 0x00010000>,
1905 <0x5f10000 0x00010000>;
1909 ti,sci-proc-ids = <0x09 0xff>;
1920 reg = <0x00 0x64800000 0x00 0x00080000>,
1921 <0x00 0x64e00000 0x00 0x0000c000>;
1925 ti,sci-proc-ids = <0x30 0xff>;
1933 reg = <0x00 0x65800000 0x00 0x00080000>,
1934 <0x00 0x65e00000 0x00 0x0000c000>;
1938 ti,sci-proc-ids = <0x31 0xff>;
1946 reg = <0x00 0x700000 0x00 0x1000>;
1953 reg = <0x00 0x2200000 0x00 0x100>;
1962 reg = <0x00 0x2210000 0x00 0x100>;
1976 reg = <0x00 0x22f0000 0x00 0x100>;
1987 reg = <0x00 0x2300000 0x00 0x100>;
1998 reg = <0x00 0x2310000 0x00 0x100>;
2009 reg = <0x00 0x23c0000 0x00 0x100>;
2020 reg = <0x00 0x23d0000 0x00 0x100>;
2031 reg = <0x00 0x23e0000 0x00 0x100>;
2042 reg = <0x00 0x23f0000 0x00 0x100>;