Lines Matching +full:mbox +full:- +full:name
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
15 bootph-all;
21 reserved_memory: reserved-memory {
22 #address-cells = <2>;
23 #size-cells = <2>;
29 no-map;
32 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
33 compatible = "shared-dma-pool";
35 no-map;
38 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
39 compatible = "shared-dma-pool";
41 no-map;
44 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
45 compatible = "shared-dma-pool";
47 no-map;
50 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
51 compatible = "shared-dma-pool";
53 no-map;
56 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
57 compatible = "shared-dma-pool";
59 no-map;
62 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
63 compatible = "shared-dma-pool";
65 no-map;
68 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
69 compatible = "shared-dma-pool";
71 no-map;
74 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
75 compatible = "shared-dma-pool";
77 no-map;
80 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
81 compatible = "shared-dma-pool";
83 no-map;
86 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
87 compatible = "shared-dma-pool";
89 no-map;
92 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
93 compatible = "shared-dma-pool";
95 no-map;
98 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
99 compatible = "shared-dma-pool";
101 no-map;
104 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
105 compatible = "shared-dma-pool";
107 no-map;
110 c66_0_memory_region: c66-memory@a6100000 {
111 compatible = "shared-dma-pool";
113 no-map;
116 c66_0_dma_memory_region: c66-dma-memory@a7000000 {
117 compatible = "shared-dma-pool";
119 no-map;
122 c66_1_memory_region: c66-memory@a7100000 {
123 compatible = "shared-dma-pool";
125 no-map;
128 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
129 compatible = "shared-dma-pool";
131 no-map;
134 c71_0_memory_region: c71-memory@a8100000 {
135 compatible = "shared-dma-pool";
137 no-map;
140 rtos_ipc_memory_region: ipc-memories@aa000000 {
143 no-map;
149 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
150 pinctrl-single,pins = <
154 bootph-all;
157 pmic_irq_pins_default: pmic-irq-default-pins {
158 pinctrl-single,pins = <
163 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
164 pinctrl-single,pins = <
177 bootph-all;
180 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
181 pinctrl-single,pins = <
197 bootph-all;
203 pinctrl-names = "default";
204 pinctrl-0 = <&wkup_i2c0_pins_default>;
205 clock-frequency = <400000>;
208 /* CAV24C256WE-GT3 */
214 compatible = "ti,tps6594-q1";
216 system-power-controller;
217 pinctrl-names = "default";
218 pinctrl-0 = <&pmic_irq_pins_default>;
219 interrupt-parent = <&wkup_gpio0>;
221 gpio-controller;
222 #gpio-cells = <2>;
223 ti,primary-pmic;
224 buck12-supply = <&vsys_3v3>;
225 buck3-supply = <&vsys_3v3>;
226 buck4-supply = <&vsys_3v3>;
227 buck5-supply = <&vsys_3v3>;
228 ldo1-supply = <&vsys_3v3>;
229 ldo2-supply = <&vsys_3v3>;
230 ldo3-supply = <&vsys_3v3>;
231 ldo4-supply = <&vsys_3v3>;
235 regulator-name = "vdd_cpu_avs";
236 regulator-min-microvolt = <600000>;
237 regulator-max-microvolt = <900000>;
238 regulator-boot-on;
239 regulator-always-on;
240 bootph-pre-ram;
244 regulator-name = "vdd_mcu_0v85";
245 regulator-min-microvolt = <850000>;
246 regulator-max-microvolt = <850000>;
247 regulator-boot-on;
248 regulator-always-on;
252 regulator-name = "vdd_ddr_1v1";
253 regulator-min-microvolt = <1100000>;
254 regulator-max-microvolt = <1100000>;
255 regulator-boot-on;
256 regulator-always-on;
260 regulator-name = "vdd_phyio_1v8";
261 regulator-min-microvolt = <1800000>;
262 regulator-max-microvolt = <1800000>;
263 regulator-boot-on;
264 regulator-always-on;
268 regulator-name = "vdd1_lpddr4_1v8";
269 regulator-min-microvolt = <1800000>;
270 regulator-max-microvolt = <1800000>;
271 regulator-boot-on;
272 regulator-always-on;
276 regulator-name = "vdd_mcuio_1v8";
277 regulator-min-microvolt = <1800000>;
278 regulator-max-microvolt = <1800000>;
279 regulator-boot-on;
280 regulator-always-on;
284 regulator-name = "vdda_dll_0v8";
285 regulator-min-microvolt = <800000>;
286 regulator-max-microvolt = <800000>;
287 regulator-boot-on;
288 regulator-always-on;
292 regulator-name = "vda_mcu_1v8";
293 regulator-min-microvolt = <1800000>;
294 regulator-max-microvolt = <1800000>;
295 regulator-boot-on;
296 regulator-always-on;
302 compatible = "ti,tps6594-q1";
304 system-power-controller;
305 interrupt-parent = <&wkup_gpio0>;
307 gpio-controller;
308 #gpio-cells = <2>;
309 buck1234-supply = <&vsys_3v3>;
310 buck5-supply = <&vsys_3v3>;
311 ldo1-supply = <&vsys_3v3>;
312 ldo2-supply = <&vsys_3v3>;
313 ldo3-supply = <&vsys_3v3>;
314 ldo4-supply = <&vsys_3v3>;
318 regulator-name = "vdd_core_0v8";
319 regulator-min-microvolt = <800000>;
320 regulator-max-microvolt = <800000>;
321 regulator-boot-on;
322 regulator-always-on;
326 regulator-name = "vdd_ram_0v85";
327 regulator-min-microvolt = <850000>;
328 regulator-max-microvolt = <850000>;
329 regulator-boot-on;
330 regulator-always-on;
334 regulator-name = "vdd_sd_dv";
335 regulator-min-microvolt = <1800000>;
336 regulator-max-microvolt = <3300000>;
337 regulator-boot-on;
338 regulator-always-on;
342 regulator-name = "vdd_usb_3v3";
343 regulator-min-microvolt = <3300000>;
344 regulator-max-microvolt = <3300000>;
345 regulator-boot-on;
346 regulator-always-on;
350 regulator-name = "vdd_io_1v8";
351 regulator-min-microvolt = <1800000>;
352 regulator-max-microvolt = <1800000>;
353 regulator-boot-on;
354 regulator-always-on;
358 regulator-name = "vda_pll_1v8";
359 regulator-min-microvolt = <1800000>;
360 regulator-max-microvolt = <1800000>;
361 regulator-boot-on;
362 regulator-always-on;
370 pinctrl-names = "default";
371 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
374 compatible = "jedec,spi-nor";
376 spi-tx-bus-width = <8>;
377 spi-rx-bus-width = <8>;
378 spi-max-frequency = <25000000>;
379 cdns,tshsl-ns = <60>;
380 cdns,tsd2d-ns = <60>;
381 cdns,tchsh-ns = <60>;
382 cdns,tslch-ns = <60>;
383 cdns,read-delay = <0>;
386 compatible = "fixed-partitions";
387 #address-cells = <1>;
388 #size-cells = <1>;
401 label = "ospi.u-boot";
428 bootph-all;
439 pinctrl-names = "default";
440 pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
445 compatible = "cypress,hyperflash", "cfi-flash";
447 bootph-all;
450 compatible = "fixed-partitions";
451 #address-cells = <1>;
452 #size-cells = <1>;
465 label = "hbmc.u-boot";
491 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
492 ti,mbox-rx = <0 0 0>;
493 ti,mbox-tx = <1 0 0>;
496 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
497 ti,mbox-rx = <2 0 0>;
498 ti,mbox-tx = <3 0 0>;
506 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
507 ti,mbox-rx = <0 0 0>;
508 ti,mbox-tx = <1 0 0>;
511 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
512 ti,mbox-rx = <2 0 0>;
513 ti,mbox-tx = <3 0 0>;
521 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
522 ti,mbox-rx = <0 0 0>;
523 ti,mbox-tx = <1 0 0>;
526 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
527 ti,mbox-rx = <2 0 0>;
528 ti,mbox-tx = <3 0 0>;
536 mbox_c66_0: mbox-c66-0 {
537 ti,mbox-rx = <0 0 0>;
538 ti,mbox-tx = <1 0 0>;
541 mbox_c66_1: mbox-c66-1 {
542 ti,mbox-rx = <2 0 0>;
543 ti,mbox-tx = <3 0 0>;
551 mbox_c71_0: mbox-c71-0 {
552 ti,mbox-rx = <0 0 0>;
553 ti,mbox-tx = <1 0 0>;
559 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
565 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
570 ti,cluster-mode = <0>;
574 ti,cluster-mode = <0>;
608 memory-region = <&main_r5fss0_core0_dma_memory_region>,
614 memory-region = <&main_r5fss0_core1_dma_memory_region>,
620 memory-region = <&main_r5fss1_core0_dma_memory_region>,
626 memory-region = <&main_r5fss1_core1_dma_memory_region>,
633 memory-region = <&c66_0_dma_memory_region>,
640 memory-region = <&c66_1_dma_memory_region>,
647 memory-region = <&c71_0_dma_memory_region>,