Lines Matching +full:r5f +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/net/ti-dp83867.h>
16 compatible = "ti,j721e-sk", "ti,j721e";
29 stdout-path = "serial2:115200n8";
34 bootph-all;
36 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
37 <0x00000008 0x80000000 0x00000000 0x80000000>;
40 reserved_memory: reserved-memory {
41 #address-cells = <2>;
42 #size-cells = <2>;
46 reg = <0x00 0x9e800000 0x00 0x01800000>;
47 alignment = <0x1000>;
48 no-map;
51 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
52 compatible = "shared-dma-pool";
53 reg = <0x00 0xa0000000 0x00 0x100000>;
54 no-map;
57 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
58 compatible = "shared-dma-pool";
59 reg = <0x00 0xa0100000 0x00 0xf00000>;
60 no-map;
63 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
64 compatible = "shared-dma-pool";
65 reg = <0x00 0xa1000000 0x00 0x100000>;
66 no-map;
69 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
70 compatible = "shared-dma-pool";
71 reg = <0x00 0xa1100000 0x00 0xf00000>;
72 no-map;
75 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
76 compatible = "shared-dma-pool";
77 reg = <0x00 0xa2000000 0x00 0x100000>;
78 no-map;
81 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
82 compatible = "shared-dma-pool";
83 reg = <0x00 0xa2100000 0x00 0xf00000>;
84 no-map;
87 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
88 compatible = "shared-dma-pool";
89 reg = <0x00 0xa3000000 0x00 0x100000>;
90 no-map;
93 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
94 compatible = "shared-dma-pool";
95 reg = <0x00 0xa3100000 0x00 0xf00000>;
96 no-map;
99 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
100 compatible = "shared-dma-pool";
101 reg = <0x00 0xa4000000 0x00 0x100000>;
102 no-map;
105 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
106 compatible = "shared-dma-pool";
107 reg = <0x00 0xa4100000 0x00 0xf00000>;
108 no-map;
111 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
112 compatible = "shared-dma-pool";
113 reg = <0x00 0xa5000000 0x00 0x100000>;
114 no-map;
117 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
118 compatible = "shared-dma-pool";
119 reg = <0x00 0xa5100000 0x00 0xf00000>;
120 no-map;
123 c66_0_dma_memory_region: c66-dma-memory@a6000000 {
124 compatible = "shared-dma-pool";
125 reg = <0x00 0xa6000000 0x00 0x100000>;
126 no-map;
129 c66_0_memory_region: c66-memory@a6100000 {
130 compatible = "shared-dma-pool";
131 reg = <0x00 0xa6100000 0x00 0xf00000>;
132 no-map;
135 c66_1_dma_memory_region: c66-dma-memory@a7000000 {
136 compatible = "shared-dma-pool";
137 reg = <0x00 0xa7000000 0x00 0x100000>;
138 no-map;
141 c66_1_memory_region: c66-memory@a7100000 {
142 compatible = "shared-dma-pool";
143 reg = <0x00 0xa7100000 0x00 0xf00000>;
144 no-map;
147 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
148 compatible = "shared-dma-pool";
149 reg = <0x00 0xa8000000 0x00 0x100000>;
150 no-map;
153 c71_0_memory_region: c71-memory@a8100000 {
154 compatible = "shared-dma-pool";
155 reg = <0x00 0xa8100000 0x00 0xf00000>;
156 no-map;
159 rtos_ipc_memory_region: ipc-memories@aa000000 {
160 reg = <0x00 0xaa000000 0x00 0x01c00000>;
161 alignment = <0x1000>;
162 no-map;
166 vusb_main: fixedregulator-vusb-main5v0 {
168 compatible = "regulator-fixed";
169 regulator-name = "vusb-main5v0";
170 regulator-min-microvolt = <5000000>;
171 regulator-max-microvolt = <5000000>;
172 regulator-always-on;
173 regulator-boot-on;
176 vsys_3v3: fixedregulator-vsys3v3 {
178 compatible = "regulator-fixed";
179 regulator-name = "vsys_3v3";
180 regulator-min-microvolt = <3300000>;
181 regulator-max-microvolt = <3300000>;
182 vin-supply = <&vusb_main>;
183 regulator-always-on;
184 regulator-boot-on;
187 vsys_5v0: fixedregulator-vsys5v0 {
189 compatible = "regulator-fixed";
190 regulator-name = "vsys_5v0";
191 regulator-min-microvolt = <5000000>;
192 regulator-max-microvolt = <5000000>;
193 vin-supply = <&vusb_main>;
194 regulator-always-on;
195 regulator-boot-on;
198 vdd_mmc1: fixedregulator-sd {
199 compatible = "regulator-fixed";
200 pinctrl-names = "default";
201 pinctrl-0 = <&vdd_mmc1_en_pins_default>;
202 regulator-name = "vdd_mmc1";
203 regulator-min-microvolt = <3300000>;
204 regulator-max-microvolt = <3300000>;
205 regulator-boot-on;
206 enable-active-high;
207 vin-supply = <&vsys_3v3>;
211 vdd_sd_dv_alt: gpio-regulator-tps659411 {
212 compatible = "regulator-gpio";
213 pinctrl-names = "default";
214 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
215 regulator-name = "tps659411";
216 regulator-min-microvolt = <1800000>;
217 regulator-max-microvolt = <3300000>;
218 regulator-boot-on;
219 vin-supply = <&vsys_3v3>;
221 states = <1800000 0x0>,
222 <3300000 0x1>;
225 vdd_sd_dv: gpio-regulator-TLV71033 {
226 compatible = "regulator-gpio";
227 pinctrl-names = "default";
228 pinctrl-0 = <&vdd_sd_dv_pins_default>;
229 regulator-name = "tlv71033";
230 regulator-min-microvolt = <1800000>;
231 regulator-max-microvolt = <3300000>;
232 regulator-boot-on;
233 vin-supply = <&vsys_5v0>;
235 states = <1800000 0x0>,
236 <3300000 0x1>;
239 transceiver1: can-phy1 {
241 #phy-cells = <0>;
242 max-bitrate = <5000000>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
245 standby-gpios = <&wkup_gpio0 3 GPIO_ACTIVE_HIGH>;
248 transceiver2: can-phy2 {
250 #phy-cells = <0>;
251 max-bitrate = <5000000>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&main_mcan0_gpio_pins_default>;
254 standby-gpios = <&main_gpio0 65 GPIO_ACTIVE_HIGH>;
257 transceiver3: can-phy3 {
259 #phy-cells = <0>;
260 max-bitrate = <5000000>;
261 pinctrl-names = "default";
262 pinctrl-0 = <&main_mcan5_gpio_pins_default>;
263 standby-gpios = <&main_gpio0 66 GPIO_ACTIVE_HIGH>;
266 transceiver4: can-phy4 {
268 #phy-cells = <0>;
269 max-bitrate = <5000000>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&main_mcan9_gpio_pins_default>;
272 standby-gpios = <&main_gpio0 67 GPIO_ACTIVE_HIGH>;
275 dp_pwr_3v3: fixedregulator-dp-prw {
276 compatible = "regulator-fixed";
277 regulator-name = "dp-pwr";
278 regulator-min-microvolt = <3300000>;
279 regulator-max-microvolt = <3300000>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&dp_pwr_en_pins_default>;
282 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */
283 enable-active-high;
287 compatible = "dp-connector";
289 type = "full-size";
290 dp-pwr-supply = <&dp_pwr_3v3>;
294 remote-endpoint = <&dp0_out>;
299 hdmi-connector {
300 compatible = "hdmi-connector";
304 pinctrl-names = "default";
305 pinctrl-0 = <&hdmi_hpd_pins_default>;
307 ddc-i2c-bus = <&main_i2c1>;
310 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>;
314 remote-endpoint = <&tfp410_out>;
319 dvi-bridge {
322 pinctrl-names = "default";
323 pinctrl-0 = <&hdmi_pdn_pins_default>;
325 powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>;
326 ti,deskew = <0>;
329 #address-cells = <1>;
330 #size-cells = <0>;
332 port@0 {
333 reg = <0>;
336 remote-endpoint = <&dpi1_out>;
337 pclk-sample = <1>;
345 remote-endpoint =
352 csi_mux: mux-controller {
353 compatible = "gpio-mux";
354 #mux-state-cells = <1>;
355 mux-gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>;
356 idle-state = <0>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&main_csi_mux_sel_pins_default>;
363 main_mmc1_pins_default: main-mmc1-default-pins {
364 pinctrl-single,pins = <
365 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
366 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
367 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
368 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
369 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
370 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
371 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
372 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
374 bootph-all;
377 main_uart0_pins_default: main-uart0-default-pins {
378 pinctrl-single,pins = <
379 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
380 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
381 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
382 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
384 bootph-all;
387 main_uart1_pins_default: main-uart1-default-pins {
388 pinctrl-single,pins = <
389 J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
390 J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
394 main_i2c0_pins_default: main-i2c0-default-pins {
395 pinctrl-single,pins = <
396 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
397 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
401 main_i2c1_pins_default: main-i2c1-default-pins {
402 pinctrl-single,pins = <
403 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
404 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
408 main_i2c3_pins_default: main-i2c3-default-pins {
409 pinctrl-single,pins = <
410 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
411 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
415 main_usbss0_pins_default: main-usbss0-default-pins {
416 pinctrl-single,pins = <
417 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
418 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
420 bootph-all;
423 main_usbss1_pins_default: main-usbss1-default-pins {
424 pinctrl-single,pins = <
425 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
427 bootph-all;
430 main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins {
431 pinctrl-single,pins = <
432 J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */
436 main_mcan0_pins_default: main-mcan0-default-pins {
437 pinctrl-single,pins = <
438 J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
439 J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
443 main_mcan0_gpio_pins_default: main-mcan0-gpio-default-pins {
444 pinctrl-single,pins = <
445 J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */
449 main_mcan5_pins_default: main-mcan5-default-pins {
450 pinctrl-single,pins = <
451 J721E_IOPAD(0x050, PIN_INPUT, 6) /* (AE21) PRG1_PRU0_GPO18.MCAN5_RX */
452 J721E_IOPAD(0x04c, PIN_OUTPUT, 6) /* (AJ21) PRG1_PRU0_GPO17.MCAN5_TX */
456 main_mcan5_gpio_pins_default: main-mcan5-gpio-default-pins {
457 pinctrl-single,pins = <
458 J721E_IOPAD(0x10c, PIN_INPUT, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */
462 main_mcan9_pins_default: main-mcan9-default-pins {
463 pinctrl-single,pins = <
464 J721E_IOPAD(0x0d0, PIN_INPUT, 6) /* (AC27) PRG0_PRU0_GPO8.MCAN9_RX */
465 J721E_IOPAD(0x0cc, PIN_OUTPUT, 6) /* (AC28) PRG0_PRU0_GPO7.MCAN9_TX */
469 main_mcan9_gpio_pins_default: main-mcan9-gpio-default-pins {
470 pinctrl-single,pins = <
471 J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */
475 dp0_pins_default: dp0-default-pins {
476 pinctrl-single,pins = <
477 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
481 dp_pwr_en_pins_default: dp-pwr-en-default-pins {
482 pinctrl-single,pins = <
483 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
487 dss_vout0_pins_default: dss-vout0-default-pins {
488 pinctrl-single,pins = <
489 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
490 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
491 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */
492 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */
493 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */
494 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */
495 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */
496 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */
497 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */
498 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */
499 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */
500 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */
501 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */
502 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */
503 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */
504 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */
505 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */
506 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */
507 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */
508 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */
509 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */
510 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */
511 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */
512 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */
513 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */
514 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */
515 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */
516 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */
520 hdmi_hpd_pins_default: hdmi-hpd-default-pins {
521 pinctrl-single,pins = <
522 J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */
526 hdmi_pdn_pins_default: hdmi-pdn-default-pins {
527 pinctrl-single,pins = <
528 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
533 ekey_reset_pins_default: ekey-reset-pns-default-pins {
534 pinctrl-single,pins = <
535 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */
539 main_i2c5_pins_default: main-i2c5-default-pins {
540 pinctrl-single,pins = <
541 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
542 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
546 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
547 pinctrl-single,pins = <
548 J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
549 J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */
550 J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
551 J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
552 J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
553 J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
554 J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
555 J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
556 J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
557 J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
558 J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */
559 J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
560 J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
561 J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
562 J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
563 J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
564 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
565 J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
566 J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
567 J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */
568 J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
569 J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
570 J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
574 rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins {
575 pinctrl-single,pins = <
576 J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */
582 pmic_irq_pins_default: pmic-irq-default-pins {
583 pinctrl-single,pins = <
584 J721E_WKUP_IOPAD(0x0cc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
588 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
589 pinctrl-single,pins = <
590 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
591 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
592 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
593 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
594 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
595 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
596 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
597 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
598 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
599 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
600 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
601 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
605 mcu_mdio_pins_default: mcu-mdio1-default-pins {
606 pinctrl-single,pins = <
607 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
608 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
612 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
613 pinctrl-single,pins = <
614 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
615 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
616 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
617 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
618 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
619 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
620 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
621 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
622 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
623 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
624 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
626 bootph-all;
629 vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
630 pinctrl-single,pins = <
631 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
635 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
636 pinctrl-single,pins = <
637 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
641 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
642 pinctrl-single,pins = <
643 J721E_IOPAD(0x1dc, PIN_OUTPUT, 7) /* (Y1) SPI1_CLK.GPIO0_118 */
647 wkup_uart0_pins_default: wkup-uart0-default-pins {
648 pinctrl-single,pins = <
649 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
650 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
654 mcu_uart0_pins_default: mcu-uart0-default-pins {
655 pinctrl-single,pins = <
656 J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
657 J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
658 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
659 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
661 bootph-all;
664 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
665 pinctrl-single,pins = <
666 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
667 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
669 bootph-all;
672 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
673 pinctrl-single,pins = <
674 J721E_WKUP_IOPAD(0x0ac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
675 J721E_WKUP_IOPAD(0x0a8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
679 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
680 pinctrl-single,pins = <
681 J721E_WKUP_IOPAD(0x0bc, PIN_INPUT, 7) /* (F27) WKUP_GPIO0_3 */
686 mkey_reset_pins_default: mkey-reset-pns-default-pins {
687 pinctrl-single,pins = <
688 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */
696 pinctrl-names = "default";
697 pinctrl-0 = <&wkup_uart0_pins_default>;
698 bootph-all;
703 pinctrl-names = "default";
704 pinctrl-0 = <&wkup_i2c0_pins_default>;
705 clock-frequency = <400000>;
708 /* AT24C512C-MAHM-T */
710 reg = <0x51>;
714 compatible = "ti,tps6594-q1";
715 reg = <0x48>;
716 system-power-controller;
717 pinctrl-names = "default";
718 pinctrl-0 = <&pmic_irq_pins_default>;
719 interrupt-parent = <&wkup_gpio0>;
721 gpio-controller;
722 #gpio-cells = <2>;
723 ti,primary-pmic;
724 buck123-supply = <&vsys_3v3>;
725 buck4-supply = <&vsys_3v3>;
726 buck5-supply = <&vsys_3v3>;
727 ldo1-supply = <&vsys_3v3>;
728 ldo2-supply = <&vsys_3v3>;
729 ldo3-supply = <&vsys_3v3>;
730 ldo4-supply = <&vsys_3v3>;
734 regulator-name = "vdd_cpu_avs";
735 regulator-min-microvolt = <600000>;
736 regulator-max-microvolt = <900000>;
737 regulator-boot-on;
738 regulator-always-on;
739 bootph-pre-ram;
743 regulator-name = "vdd_mcu_0v85";
744 regulator-min-microvolt = <850000>;
745 regulator-max-microvolt = <850000>;
746 regulator-boot-on;
747 regulator-always-on;
751 regulator-name = "vdd_phyio_1v8";
752 regulator-min-microvolt = <1800000>;
753 regulator-max-microvolt = <1800000>;
754 regulator-boot-on;
755 regulator-always-on;
759 regulator-name = "vdd1_lpddr4_1v8";
760 regulator-min-microvolt = <1800000>;
761 regulator-max-microvolt = <1800000>;
762 regulator-boot-on;
763 regulator-always-on;
767 regulator-name = "vdd_mcuio_1v8";
768 regulator-min-microvolt = <1800000>;
769 regulator-max-microvolt = <1800000>;
770 regulator-boot-on;
771 regulator-always-on;
775 regulator-name = "vdda_dll_0v8";
776 regulator-min-microvolt = <800000>;
777 regulator-max-microvolt = <800000>;
778 regulator-boot-on;
779 regulator-always-on;
783 regulator-name = "vda_mcu_1v8";
784 regulator-min-microvolt = <1800000>;
785 regulator-max-microvolt = <1800000>;
786 regulator-boot-on;
787 regulator-always-on;
793 compatible = "ti,tps6594-q1";
794 reg = <0x4c>;
795 system-power-controller;
796 interrupt-parent = <&wkup_gpio0>;
798 gpio-controller;
799 #gpio-cells = <2>;
800 buck1234-supply = <&vsys_3v3>;
801 buck5-supply = <&vsys_3v3>;
802 ldo1-supply = <&vsys_3v3>;
803 ldo2-supply = <&vsys_3v3>;
804 ldo3-supply = <&vsys_3v3>;
805 ldo4-supply = <&vsys_3v3>;
809 regulator-name = "vdd_core_0v8";
810 regulator-min-microvolt = <800000>;
811 regulator-max-microvolt = <800000>;
812 regulator-boot-on;
813 regulator-always-on;
817 regulator-name = "vdd_ram_0v85";
818 regulator-min-microvolt = <850000>;
819 regulator-max-microvolt = <850000>;
820 regulator-boot-on;
821 regulator-always-on;
825 regulator-name = "vdd_sd_dv";
826 regulator-min-microvolt = <1800000>;
827 regulator-max-microvolt = <3300000>;
828 regulator-boot-on;
829 regulator-always-on;
833 regulator-name = "vdd_usb_3v3";
834 regulator-min-microvolt = <3300000>;
835 regulator-max-microvolt = <3300000>;
836 regulator-boot-on;
837 regulator-always-on;
841 regulator-name = "vdd_io_1v8";
842 regulator-min-microvolt = <1800000>;
843 regulator-max-microvolt = <1800000>;
844 regulator-boot-on;
845 regulator-always-on;
849 regulator-name = "vda_pll_1v8";
850 regulator-min-microvolt = <1800000>;
851 regulator-max-microvolt = <1800000>;
852 regulator-boot-on;
853 regulator-always-on;
861 pinctrl-names = "default";
862 pinctrl-0 = <&mcu_uart0_pins_default>;
863 bootph-all;
868 pinctrl-names = "default";
869 pinctrl-0 = <&main_uart0_pins_default>;
871 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
872 bootph-all;
877 pinctrl-names = "default";
878 pinctrl-0 = <&main_uart1_pins_default>;
884 vmmc-supply = <&vdd_mmc1>;
885 vqmmc-supply = <&vdd_sd_dv_alt>;
886 pinctrl-names = "default";
887 pinctrl-0 = <&main_mmc1_pins_default>;
888 bootph-all;
889 ti,driver-strength-ohm = <50>;
890 disable-wp;
895 pinctrl-names = "default";
896 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
898 flash@0 {
899 compatible = "jedec,spi-nor";
900 reg = <0x0>;
901 spi-tx-bus-width = <8>;
902 spi-rx-bus-width = <8>;
903 spi-max-frequency = <25000000>;
904 cdns,tshsl-ns = <60>;
905 cdns,tsd2d-ns = <60>;
906 cdns,tchsh-ns = <60>;
907 cdns,tslch-ns = <60>;
908 cdns,read-delay = <4>;
911 compatible = "fixed-partitions";
912 #address-cells = <1>;
913 #size-cells = <1>;
915 partition@0 {
917 reg = <0x0 0x80000>;
922 reg = <0x80000 0x200000>;
926 label = "ospi.u-boot";
927 reg = <0x280000 0x400000>;
932 reg = <0x680000 0x40000>;
937 reg = <0x6c0000 0x100000>;
942 reg = <0x7c0000 0x40000>;
947 reg = <0x800000 0x37c0000>;
952 reg = <0x3fc0000 0x40000>;
953 bootph-all;
961 pinctrl-names = "default";
962 pinctrl-0 = <&main_i2c0_pins_default>;
963 clock-frequency = <400000>;
965 i2c-mux@71 {
967 #address-cells = <1>;
968 #size-cells = <0>;
969 reg = <0x71>;
972 i2c@0 {
973 #address-cells = <1>;
974 #size-cells = <0>;
975 reg = <0>;
980 #address-cells = <1>;
981 #size-cells = <0>;
989 pinctrl-names = "default";
990 pinctrl-0 = <&main_i2c1_pins_default>;
992 clock-frequency = <100000>;
997 pinctrl-names = "default";
998 pinctrl-0 = <&main_i2c3_pins_default>;
999 clock-frequency = <400000>;
1001 i2c-mux@70 {
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 reg = <0x70>;
1008 cam0_i2c: i2c@0 {
1009 #address-cells = <1>;
1010 #size-cells = <0>;
1011 reg = <0>;
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1026 pinctrl-names = "default";
1027 pinctrl-0 = <&main_i2c5_pins_default>;
1028 clock-frequency = <400000>;
1033 pinctrl-names = "default";
1034 pinctrl-0 = <&rpi_header_gpio0_pins_default>;
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&rpi_header_gpio1_pins_default>;
1048 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
1049 bootph-all;
1053 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
1059 bootph-all;
1063 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
1064 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
1068 serdes3_usb_link: phy@0 {
1069 reg = <0>;
1070 cdns,num-lanes = <2>;
1071 #phy-cells = <0>;
1072 cdns,phy-type = <PHY_TYPE_USB3>;
1074 bootph-all;
1079 torrent_phy_dp: phy@0 {
1080 reg = <0>;
1082 cdns,phy-type = <PHY_TYPE_DP>;
1083 cdns,num-lanes = <4>;
1084 cdns,max-bit-rate = <5400>;
1085 #phy-cells = <0>;
1091 phy-names = "dpphy";
1092 pinctrl-names = "default";
1093 pinctrl-0 = <&dp0_pins_default>;
1097 pinctrl-names = "default";
1098 pinctrl-0 = <&main_usbss0_pins_default>;
1099 bootph-all;
1100 ti,vbus-divider;
1105 maximum-speed = "super-speed";
1107 phy-names = "cdns3,usb3-phy";
1108 bootph-all;
1114 cdns,num-lanes = <1>;
1115 #phy-cells = <0>;
1116 cdns,phy-type = <PHY_TYPE_USB3>;
1122 pinctrl-names = "default";
1123 pinctrl-0 = <&main_usbss1_pins_default>;
1124 bootph-all;
1125 ti,vbus-divider;
1130 maximum-speed = "super-speed";
1132 phy-names = "cdns3,usb3-phy";
1133 bootph-all;
1137 pinctrl-names = "default";
1138 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
1142 phy0: ethernet-phy@0 {
1143 reg = <0>;
1144 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
1145 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
1150 phy-mode = "rgmii-rxid";
1151 phy-handle = <&phy0>;
1155 pinctrl-names = "default";
1156 pinctrl-0 = <&dss_vout0_pins_default>;
1158 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
1162 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1172 port@0 {
1173 reg = <0>;
1176 remote-endpoint = <&dp0_in>;
1184 remote-endpoint = <&tfp410_in>;
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1193 port@0 {
1194 reg = <0>;
1196 remote-endpoint = <&dpi0_out>;
1203 remote-endpoint = <&dp_connector_in>;
1209 serdes0_pcie_link: phy@0 {
1210 reg = <0>;
1211 cdns,num-lanes = <1>;
1212 #phy-cells = <0>;
1213 cdns,phy-type = <PHY_TYPE_PCIE>;
1219 serdes1_pcie_link: phy@0 {
1220 reg = <0>;
1221 cdns,num-lanes = <2>;
1222 #phy-cells = <0>;
1223 cdns,phy-type = <PHY_TYPE_PCIE>;
1230 pinctrl-names = "default";
1231 pinctrl-0 = <&ekey_reset_pins_default>;
1232 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>;
1235 phy-names = "pcie-phy";
1236 num-lanes = <1>;
1241 pinctrl-names = "default";
1242 pinctrl-0 = <&mkey_reset_pins_default>;
1243 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
1246 phy-names = "pcie-phy";
1247 num-lanes = <2>;
1251 pinctrl-names = "default";
1252 pinctrl-0 = <&mcu_mcan0_pins_default>;
1258 pinctrl-names = "default";
1259 pinctrl-0 = <&main_mcan0_pins_default>;
1265 pinctrl-names = "default";
1266 pinctrl-0 = <&main_mcan5_pins_default>;
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&main_mcan9_pins_default>;
1286 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
1287 ti,mbox-rx = <0 0 0>;
1288 ti,mbox-tx = <1 0 0>;
1291 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
1292 ti,mbox-rx = <2 0 0>;
1293 ti,mbox-tx = <3 0 0>;
1301 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
1302 ti,mbox-rx = <0 0 0>;
1303 ti,mbox-tx = <1 0 0>;
1306 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
1307 ti,mbox-rx = <2 0 0>;
1308 ti,mbox-tx = <3 0 0>;
1316 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
1317 ti,mbox-rx = <0 0 0>;
1318 ti,mbox-tx = <1 0 0>;
1321 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
1322 ti,mbox-rx = <2 0 0>;
1323 ti,mbox-tx = <3 0 0>;
1331 mbox_c66_0: mbox-c66-0 {
1332 ti,mbox-rx = <0 0 0>;
1333 ti,mbox-tx = <1 0 0>;
1336 mbox_c66_1: mbox-c66-1 {
1337 ti,mbox-rx = <2 0 0>;
1338 ti,mbox-tx = <3 0 0>;
1346 mbox_c71_0: mbox-c71-0 {
1347 ti,mbox-rx = <0 0 0>;
1348 ti,mbox-tx = <1 0 0>;
1354 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
1360 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
1365 ti,cluster-mode = <0>;
1369 ti,cluster-mode = <0>;
1403 memory-region = <&main_r5fss0_core0_dma_memory_region>,
1409 memory-region = <&main_r5fss0_core1_dma_memory_region>,
1415 memory-region = <&main_r5fss1_core0_dma_memory_region>,
1421 memory-region = <&main_r5fss1_core1_dma_memory_region>,
1428 memory-region = <&c66_0_dma_memory_region>,
1435 memory-region = <&c66_1_dma_memory_region>,
1442 memory-region = <&c71_0_dma_memory_region>,