Lines Matching +full:am654 +full:- +full:navss +full:- +full:ringacc
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
24 bootph-all;
27 k3_clks: clock-controller {
28 compatible = "ti,k2g-sci-clk";
29 #clock-cells = <2>;
30 bootph-all;
33 k3_reset: reset-controller {
34 compatible = "ti,sci-reset";
35 #reset-cells = <2>;
36 bootph-all;
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
46 cpsw_mac_syscon: ethernet-mac-syscon@200 {
47 compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
52 compatible = "ti,am654-phy-gmii-sel";
54 #phy-cells = <1>;
59 compatible = "simple-bus";
60 #address-cells = <1>;
61 #size-cells = <1>;
65 compatible = "ti,am654-chipid";
67 bootph-all;
72 compatible = "pinctrl-single";
75 #pinctrl-cells = <1>;
76 pinctrl-single,register-width = <32>;
77 pinctrl-single,function-mask = <0xffffffff>;
82 compatible = "pinctrl-single";
84 #pinctrl-cells = <1>;
85 pinctrl-single,register-width = <32>;
86 pinctrl-single,function-mask = <0x0000000f>;
87 /* Non-MPU Firmware usage */
93 compatible = "pinctrl-single";
95 #pinctrl-cells = <1>;
96 pinctrl-single,register-width = <32>;
97 pinctrl-single,function-mask = <0x0000000f>;
98 /* Non-MPU Firmware usage */
103 compatible = "mmio-sram";
106 #address-cells = <1>;
107 #size-cells = <1>;
111 compatible = "ti,am654-timer";
115 clock-names = "fck";
116 assigned-clocks = <&k3_clks 35 1>;
117 assigned-clock-parents = <&k3_clks 35 2>;
118 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
119 bootph-pre-ram;
120 ti,timer-pwm;
121 /* Non-MPU Firmware usage */
126 compatible = "ti,am654-timer";
130 clock-names = "fck";
131 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
132 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>;
133 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
134 ti,timer-pwm;
135 /* Non-MPU Firmware usage */
140 compatible = "ti,am654-timer";
144 clock-names = "fck";
145 assigned-clocks = <&k3_clks 72 1>;
146 assigned-clock-parents = <&k3_clks 72 2>;
147 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
148 ti,timer-pwm;
149 /* Non-MPU Firmware usage */
154 compatible = "ti,am654-timer";
158 clock-names = "fck";
159 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
160 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>;
161 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
162 ti,timer-pwm;
163 /* Non-MPU Firmware usage */
168 compatible = "ti,am654-timer";
172 clock-names = "fck";
173 assigned-clocks = <&k3_clks 74 1>;
174 assigned-clock-parents = <&k3_clks 74 2>;
175 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
176 ti,timer-pwm;
177 /* Non-MPU Firmware usage */
182 compatible = "ti,am654-timer";
186 clock-names = "fck";
187 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>;
188 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>;
189 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
190 ti,timer-pwm;
191 /* Non-MPU Firmware usage */
196 compatible = "ti,am654-timer";
200 clock-names = "fck";
201 assigned-clocks = <&k3_clks 76 1>;
202 assigned-clock-parents = <&k3_clks 76 2>;
203 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
204 ti,timer-pwm;
205 /* Non-MPU Firmware usage */
210 compatible = "ti,am654-timer";
214 clock-names = "fck";
215 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>;
216 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>;
217 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
218 ti,timer-pwm;
219 /* Non-MPU Firmware usage */
224 compatible = "ti,am654-timer";
228 clock-names = "fck";
229 assigned-clocks = <&k3_clks 78 1>;
230 assigned-clock-parents = <&k3_clks 78 2>;
231 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
232 ti,timer-pwm;
233 /* Non-MPU Firmware usage */
238 compatible = "ti,am654-timer";
242 clock-names = "fck";
243 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>;
244 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>;
245 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
246 ti,timer-pwm;
247 /* Non-MPU Firmware usage */
251 compatible = "ti,j721e-uart", "ti,am654-uart";
254 clock-frequency = <48000000>;
255 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
257 clock-names = "fclk";
262 compatible = "ti,j721e-uart", "ti,am654-uart";
265 clock-frequency = <96000000>;
266 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
268 clock-names = "fclk";
272 wkup_gpio_intr: interrupt-controller@42200000 {
273 compatible = "ti,sci-intr";
275 ti,intr-trigger-type = <1>;
276 interrupt-controller;
277 interrupt-parent = <&gic500>;
278 #interrupt-cells = <1>;
280 ti,sci-dev-id = <137>;
281 ti,interrupt-ranges = <16 960 16>;
285 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
287 gpio-controller;
288 #gpio-cells = <2>;
289 interrupt-parent = <&wkup_gpio_intr>;
291 interrupt-controller;
292 #interrupt-cells = <2>;
294 ti,davinci-gpio-unbanked = <0>;
295 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
297 clock-names = "gpio";
302 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
304 gpio-controller;
305 #gpio-cells = <2>;
306 interrupt-parent = <&wkup_gpio_intr>;
308 interrupt-controller;
309 #interrupt-cells = <2>;
311 ti,davinci-gpio-unbanked = <0>;
312 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
314 clock-names = "gpio";
319 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
322 #address-cells = <1>;
323 #size-cells = <0>;
324 clock-names = "fck";
326 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
331 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
334 #address-cells = <1>;
335 #size-cells = <0>;
336 clock-names = "fck";
338 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
343 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
346 #address-cells = <1>;
347 #size-cells = <0>;
348 clock-names = "fck";
350 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
355 compatible = "simple-bus";
356 #address-cells = <2>;
357 #size-cells = <2>;
365 hbmc_mux: mux-controller@47000004 {
366 compatible = "reg-mux";
368 #mux-control-cells = <1>;
369 mux-reg-masks = <0x0 0x2>; /* HBMC select */
370 bootph-all;
374 compatible = "ti,am654-hbmc";
377 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
379 assigned-clocks = <&k3_clks 102 5>;
380 assigned-clock-rates = <333333333>;
381 #address-cells = <2>;
382 #size-cells = <1>;
383 mux-controls = <&hbmc_mux 0>;
388 compatible = "ti,am654-ospi", "cdns,qspi-nor";
392 cdns,fifo-depth = <256>;
393 cdns,fifo-width = <4>;
394 cdns,trigger-address = <0x0>;
396 assigned-clocks = <&k3_clks 103 0>;
397 assigned-clock-parents = <&k3_clks 103 2>;
398 assigned-clock-rates = <166666666>;
399 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
400 #address-cells = <1>;
401 #size-cells = <0>;
406 compatible = "ti,am654-ospi", "cdns,qspi-nor";
410 cdns,fifo-depth = <256>;
411 cdns,fifo-width = <4>;
412 cdns,trigger-address = <0x0>;
414 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
415 #address-cells = <1>;
416 #size-cells = <0>;
422 compatible = "ti,am3359-tscadc";
425 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
427 assigned-clocks = <&k3_clks 0 3>;
428 assigned-clock-rates = <60000000>;
429 clock-names = "fck";
432 dma-names = "fifo0", "fifo1";
436 #io-channel-cells = <1>;
437 compatible = "ti,am3359-adc";
442 compatible = "ti,am3359-tscadc";
445 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
447 assigned-clocks = <&k3_clks 1 3>;
448 assigned-clock-rates = <60000000>;
449 clock-names = "fck";
452 dma-names = "fifo0", "fifo1";
456 #io-channel-cells = <1>;
457 compatible = "ti,am3359-adc";
462 compatible = "simple-bus";
463 #address-cells = <2>;
464 #size-cells = <2>;
466 dma-coherent;
467 dma-ranges;
469 ti,sci-dev-id = <232>;
471 mcu_ringacc: ringacc@2b800000 {
472 compatible = "ti,am654-navss-ringacc";
478 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
479 bootph-all;
480 ti,num-rings = <286>;
481 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
483 ti,sci-dev-id = <235>;
484 msi-parent = <&main_udmass_inta>;
487 mcu_udmap: dma-controller@285c0000 {
488 compatible = "ti,j721e-navss-mcu-udmap";
495 reg-names = "gcfg", "rchanrt", "tchanrt",
497 msi-parent = <&main_udmass_inta>;
498 #dma-cells = <1>;
499 bootph-all;
502 ti,sci-dev-id = <236>;
503 ti,ringacc = <&mcu_ringacc>;
505 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
507 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
509 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
514 compatible = "ti,am654-secure-proxy";
515 #mbox-cells = <1>;
516 reg-names = "target_data", "rt", "scfg";
520 bootph-pre-ram;
524 * firmware on non-MPU processors
530 compatible = "ti,j721e-cpsw-nuss";
531 #address-cells = <2>;
532 #size-cells = <2>;
534 reg-names = "cpsw_nuss";
536 dma-coherent;
538 clock-names = "fck";
539 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
550 dma-names = "tx0", "tx1", "tx2", "tx3",
554 ethernet-ports {
555 #address-cells = <1>;
556 #size-cells = <0>;
560 ti,mac-only;
562 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
568 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
570 #address-cells = <1>;
571 #size-cells = <0>;
573 clock-names = "fck";
578 compatible = "ti,am65-cpts";
581 clock-names = "cpts";
582 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
583 interrupt-names = "cpts";
584 ti,cpts-ext-ts-inputs = <4>;
585 ti,cpts-periodic-outputs = <2>;
590 compatible = "ti,j721e-r5fss";
591 ti,cluster-mode = <1>;
592 #address-cells = <1>;
593 #size-cells = <1>;
596 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
599 compatible = "ti,j721e-r5f";
602 reg-names = "atcm", "btcm";
604 ti,sci-dev-id = <250>;
605 ti,sci-proc-ids = <0x01 0xff>;
607 firmware-name = "j7-mcu-r5f0_0-fw";
608 ti,atcm-enable = <1>;
609 ti,btcm-enable = <1>;
614 compatible = "ti,j721e-r5f";
617 reg-names = "atcm", "btcm";
619 ti,sci-dev-id = <251>;
620 ti,sci-proc-ids = <0x02 0xff>;
622 firmware-name = "j7-mcu-r5f0_1-fw";
623 ti,atcm-enable = <1>;
624 ti,btcm-enable = <1>;
633 reg-names = "m_can", "message_ram";
634 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
636 clock-names = "hclk", "cclk";
639 interrupt-names = "int0", "int1";
640 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
648 reg-names = "m_can", "message_ram";
649 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
651 clock-names = "hclk", "cclk";
654 interrupt-names = "int0", "int1";
655 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
660 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
663 #address-cells = <1>;
664 #size-cells = <0>;
665 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
671 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
674 #address-cells = <1>;
675 #size-cells = <0>;
676 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
682 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
685 #address-cells = <1>;
686 #size-cells = <0>;
687 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
692 wkup_vtm0: temperature-sensor@42040000 {
693 compatible = "ti,j721e-vtm";
697 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
698 #thermal-sensor-cells = <1>;
699 bootph-pre-ram;
703 compatible = "ti,j721e-esm";
705 ti,esm-pins = <95>;
706 bootph-pre-ram;