Lines Matching +full:0 +full:xf007
19 reg = <0x00 0x44083000 0x0 0x1000>;
41 ranges = <0x0 0x0 0x40f00000 0x20000>;
45 reg = <0x200 0x8>;
50 reg = <0x4040 0x4>;
59 ranges = <0x0 0x00 0x43000000 0x20000>;
63 reg = <0x14 0x4>;
69 /* Proxy 0 addressing */
70 reg = <0x00 0x4301c000 0x00 0x178>;
73 pinctrl-single,function-mask = <0xffffffff>;
79 reg = <0x00 0x40f04200 0x00 0x28>;
82 pinctrl-single,function-mask = <0x0000000f>;
90 reg = <0x00 0x40f04280 0x00 0x28>;
93 pinctrl-single,function-mask = <0x0000000f>;
100 reg = <0x00 0x41c00000 0x00 0x100000>;
101 ranges = <0x0 0x00 0x41c00000 0x100000>;
108 reg = <0x00 0x40400000 0x00 0x400>;
122 reg = <0x00 0x40410000 0x00 0x400>;
126 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
136 reg = <0x00 0x40420000 0x00 0x400>;
150 reg = <0x00 0x40430000 0x00 0x400>;
154 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
164 reg = <0x00 0x40440000 0x00 0x400>;
178 reg = <0x00 0x40450000 0x00 0x400>;
182 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>;
192 reg = <0x00 0x40460000 0x00 0x400>;
206 reg = <0x00 0x40470000 0x00 0x400>;
210 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>;
220 reg = <0x00 0x40480000 0x00 0x400>;
234 reg = <0x00 0x40490000 0x00 0x400>;
238 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>;
247 reg = <0x00 0x42300000 0x00 0x100>;
251 clocks = <&k3_clks 287 0>;
258 reg = <0x00 0x40a00000 0x00 0x100>;
262 clocks = <&k3_clks 149 0>;
269 reg = <0x00 0x42200000 0x00 0x400>;
281 reg = <0x0 0x42110000 0x0 0x100>;
289 ti,davinci-gpio-unbanked = <0>;
291 clocks = <&k3_clks 113 0>;
298 reg = <0x0 0x42100000 0x0 0x100>;
306 ti,davinci-gpio-unbanked = <0>;
308 clocks = <&k3_clks 114 0>;
315 reg = <0x0 0x40b00000 0x0 0x100>;
318 #size-cells = <0>;
320 clocks = <&k3_clks 194 0>;
327 reg = <0x0 0x40b10000 0x0 0x100>;
330 #size-cells = <0>;
332 clocks = <&k3_clks 195 0>;
339 reg = <0x0 0x42120000 0x0 0x100>;
342 #size-cells = <0>;
344 clocks = <&k3_clks 197 0>;
353 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */
354 <0x0 0x47034000 0x0 0x47034000 0x0 0x100>, /* HBMC Control */
355 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */
356 <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */
357 <0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>, /* FSS data region 1 */
358 <0x4 0x00000000 0x4 0x00000000 0x4 0x00000000>; /* FSS data region 0/3 */
362 reg = <0x00 0x47000004 0x00 0x4>;
364 mux-reg-masks = <0x0 0x2>; /* HBMC select */
369 reg = <0x00 0x47034000 0x00 0x100>,
370 <0x05 0x00000000 0x01 0x00000000>;
372 clocks = <&k3_clks 102 0>;
377 mux-controls = <&hbmc_mux 0>;
383 reg = <0x0 0x47040000 0x0 0x100>,
384 <0x5 0x00000000 0x1 0x00000000>;
388 cdns,trigger-address = <0x0>;
389 clocks = <&k3_clks 103 0>;
390 assigned-clocks = <&k3_clks 103 0>;
395 #size-cells = <0>;
401 reg = <0x0 0x47050000 0x0 0x100>,
402 <0x7 0x00000000 0x1 0x00000000>;
406 cdns,trigger-address = <0x0>;
407 clocks = <&k3_clks 104 0>;
410 #size-cells = <0>;
417 reg = <0x0 0x40200000 0x0 0x1000>;
419 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
420 clocks = <&k3_clks 0 1>;
421 assigned-clocks = <&k3_clks 0 3>;
424 dmas = <&main_udmap 0x7400>,
425 <&main_udmap 0x7401>;
437 reg = <0x0 0x40210000 0x0 0x1000>;
444 dmas = <&main_udmap 0x7402>,
445 <&main_udmap 0x7403>;
459 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
467 reg = <0x0 0x2b800000 0x0 0x400000>,
468 <0x0 0x2b000000 0x0 0x400000>,
469 <0x0 0x28590000 0x0 0x100>,
470 <0x0 0x2a500000 0x0 0x40000>,
471 <0x0 0x28440000 0x0 0x40000>;
474 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
482 reg = <0x0 0x285c0000 0x0 0x100>,
483 <0x0 0x2a800000 0x0 0x40000>,
484 <0x0 0x2aa00000 0x0 0x40000>,
485 <0x0 0x284a0000 0x0 0x4000>,
486 <0x0 0x284c0000 0x0 0x4000>,
487 <0x0 0x28400000 0x0 0x2000>;
497 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
498 <0x0f>; /* TX_HCHAN */
499 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
500 <0x0b>; /* RX_HCHAN */
501 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
509 reg = <0x0 0x2a480000 0x0 0x80000>,
510 <0x0 0x2a380000 0x0 0x80000>,
511 <0x0 0x2a400000 0x0 0x80000>;
524 reg = <0x0 0x46000000 0x0 0x200000>;
526 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
532 dmas = <&mcu_udmap 0xf000>,
533 <&mcu_udmap 0xf001>,
534 <&mcu_udmap 0xf002>,
535 <&mcu_udmap 0xf003>,
536 <&mcu_udmap 0xf004>,
537 <&mcu_udmap 0xf005>,
538 <&mcu_udmap 0xf006>,
539 <&mcu_udmap 0xf007>,
540 <&mcu_udmap 0x7000>;
547 #size-cells = <0>;
553 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
560 reg = <0x0 0xf00 0x0 0x100>;
562 #size-cells = <0>;
570 reg = <0x0 0x3d000 0x0 0x400>;
585 ranges = <0x41000000 0x00 0x41000000 0x20000>,
586 <0x41400000 0x00 0x41400000 0x20000>;
591 reg = <0x41000000 0x00008000>,
592 <0x41010000 0x00008000>;
596 ti,sci-proc-ids = <0x01 0xff>;
606 reg = <0x41400000 0x00008000>,
607 <0x41410000 0x00008000>;
611 ti,sci-proc-ids = <0x02 0xff>;
622 reg = <0x00 0x40528000 0x00 0x200>,
623 <0x00 0x40500000 0x00 0x8000>;
626 clocks = <&k3_clks 172 0>, <&k3_clks 172 1>;
631 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
637 reg = <0x00 0x40568000 0x00 0x200>,
638 <0x00 0x40540000 0x00 0x8000>;
641 clocks = <&k3_clks 173 0>, <&k3_clks 173 1>;
646 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
652 reg = <0x00 0x040300000 0x00 0x400>;
655 #size-cells = <0>;
657 clocks = <&k3_clks 274 0>;
663 reg = <0x00 0x040310000 0x00 0x400>;
666 #size-cells = <0>;
668 clocks = <&k3_clks 275 0>;
674 reg = <0x00 0x040320000 0x00 0x400>;
677 #size-cells = <0>;
679 clocks = <&k3_clks 276 0>;
685 reg = <0x00 0x42040000 0x00 0x350>,
686 <0x00 0x42050000 0x00 0x350>,
687 <0x00 0x43000300 0x00 0x10>;
694 reg = <0x00 0x40800000 0x00 0x1000>;