Lines Matching +full:0 +full:x41010000
19 reg = <0x00 0x44083000 0x0 0x1000>;
44 ranges = <0x0 0x0 0x40f00000 0x20000>;
48 reg = <0x200 0x8>;
53 reg = <0x4040 0x4>;
62 ranges = <0x0 0x00 0x43000000 0x20000>;
66 reg = <0x14 0x4>;
73 /* Proxy 0 addressing */
74 reg = <0x00 0x4301c000 0x00 0x178>;
77 pinctrl-single,function-mask = <0xffffffff>;
83 reg = <0x00 0x40f04200 0x00 0x28>;
86 pinctrl-single,function-mask = <0x0000000f>;
94 reg = <0x00 0x40f04280 0x00 0x28>;
97 pinctrl-single,function-mask = <0x0000000f>;
104 reg = <0x00 0x41c00000 0x00 0x100000>;
105 ranges = <0x0 0x00 0x41c00000 0x100000>;
112 reg = <0x00 0x40400000 0x00 0x400>;
127 reg = <0x00 0x40410000 0x00 0x400>;
131 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
141 reg = <0x00 0x40420000 0x00 0x400>;
155 reg = <0x00 0x40430000 0x00 0x400>;
159 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
169 reg = <0x00 0x40440000 0x00 0x400>;
183 reg = <0x00 0x40450000 0x00 0x400>;
187 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>;
197 reg = <0x00 0x40460000 0x00 0x400>;
211 reg = <0x00 0x40470000 0x00 0x400>;
215 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>;
225 reg = <0x00 0x40480000 0x00 0x400>;
239 reg = <0x00 0x40490000 0x00 0x400>;
243 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>;
252 reg = <0x00 0x42300000 0x00 0x100>;
256 clocks = <&k3_clks 287 0>;
263 reg = <0x00 0x40a00000 0x00 0x100>;
267 clocks = <&k3_clks 149 0>;
274 reg = <0x00 0x42200000 0x00 0x400>;
286 reg = <0x0 0x42110000 0x0 0x100>;
294 ti,davinci-gpio-unbanked = <0>;
296 clocks = <&k3_clks 113 0>;
303 reg = <0x0 0x42100000 0x0 0x100>;
311 ti,davinci-gpio-unbanked = <0>;
313 clocks = <&k3_clks 114 0>;
320 reg = <0x0 0x40b00000 0x0 0x100>;
323 #size-cells = <0>;
325 clocks = <&k3_clks 194 0>;
332 reg = <0x0 0x40b10000 0x0 0x100>;
335 #size-cells = <0>;
337 clocks = <&k3_clks 195 0>;
344 reg = <0x0 0x42120000 0x0 0x100>;
347 #size-cells = <0>;
349 clocks = <&k3_clks 197 0>;
358 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */
359 <0x0 0x47034000 0x0 0x47034000 0x0 0x100>, /* HBMC Control */
360 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */
361 <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */
362 <0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>, /* FSS data region 1 */
363 <0x4 0x00000000 0x4 0x00000000 0x4 0x00000000>; /* FSS data region 0/3 */
367 reg = <0x00 0x47000004 0x00 0x4>;
369 mux-reg-masks = <0x0 0x2>; /* HBMC select */
375 reg = <0x00 0x47034000 0x00 0x100>,
376 <0x05 0x00000000 0x01 0x00000000>;
378 clocks = <&k3_clks 102 0>;
383 mux-controls = <&hbmc_mux 0>;
389 reg = <0x0 0x47040000 0x0 0x100>,
390 <0x5 0x00000000 0x1 0x00000000>;
394 cdns,trigger-address = <0x0>;
395 clocks = <&k3_clks 103 0>;
396 assigned-clocks = <&k3_clks 103 0>;
401 #size-cells = <0>;
407 reg = <0x0 0x47050000 0x0 0x100>,
408 <0x7 0x00000000 0x1 0x00000000>;
412 cdns,trigger-address = <0x0>;
413 clocks = <&k3_clks 104 0>;
416 #size-cells = <0>;
423 reg = <0x0 0x40200000 0x0 0x1000>;
425 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
426 clocks = <&k3_clks 0 1>;
427 assigned-clocks = <&k3_clks 0 3>;
430 dmas = <&main_udmap 0x7400>,
431 <&main_udmap 0x7401>;
443 reg = <0x0 0x40210000 0x0 0x1000>;
450 dmas = <&main_udmap 0x7402>,
451 <&main_udmap 0x7403>;
465 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
473 reg = <0x0 0x2b800000 0x0 0x400000>,
474 <0x0 0x2b000000 0x0 0x400000>,
475 <0x0 0x28590000 0x0 0x100>,
476 <0x0 0x2a500000 0x0 0x40000>,
477 <0x0 0x28440000 0x0 0x40000>;
481 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
489 reg = <0x0 0x285c0000 0x0 0x100>,
490 <0x0 0x2a800000 0x0 0x40000>,
491 <0x0 0x2aa00000 0x0 0x40000>,
492 <0x0 0x284a0000 0x0 0x4000>,
493 <0x0 0x284c0000 0x0 0x4000>,
494 <0x0 0x28400000 0x0 0x2000>;
505 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
506 <0x0f>; /* TX_HCHAN */
507 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
508 <0x0b>; /* RX_HCHAN */
509 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
517 reg = <0x0 0x2a480000 0x0 0x80000>,
518 <0x0 0x2a380000 0x0 0x80000>,
519 <0x0 0x2a400000 0x0 0x80000>;
533 reg = <0x0 0x46000000 0x0 0x200000>;
535 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
541 dmas = <&mcu_udmap 0xf000>,
542 <&mcu_udmap 0xf001>,
543 <&mcu_udmap 0xf002>,
544 <&mcu_udmap 0xf003>,
545 <&mcu_udmap 0xf004>,
546 <&mcu_udmap 0xf005>,
547 <&mcu_udmap 0xf006>,
548 <&mcu_udmap 0xf007>,
549 <&mcu_udmap 0x7000>;
556 #size-cells = <0>;
562 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
569 reg = <0x0 0xf00 0x0 0x100>;
571 #size-cells = <0>;
579 reg = <0x0 0x3d000 0x0 0x400>;
594 ranges = <0x41000000 0x00 0x41000000 0x20000>,
595 <0x41400000 0x00 0x41400000 0x20000>;
600 reg = <0x41000000 0x00008000>,
601 <0x41010000 0x00008000>;
605 ti,sci-proc-ids = <0x01 0xff>;
615 reg = <0x41400000 0x00008000>,
616 <0x41410000 0x00008000>;
620 ti,sci-proc-ids = <0x02 0xff>;
631 reg = <0x00 0x40528000 0x00 0x200>,
632 <0x00 0x40500000 0x00 0x8000>;
635 clocks = <&k3_clks 172 0>, <&k3_clks 172 1>;
640 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
646 reg = <0x00 0x40568000 0x00 0x200>,
647 <0x00 0x40540000 0x00 0x8000>;
650 clocks = <&k3_clks 173 0>, <&k3_clks 173 1>;
655 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
661 reg = <0x00 0x040300000 0x00 0x400>;
664 #size-cells = <0>;
672 reg = <0x00 0x040310000 0x00 0x400>;
675 #size-cells = <0>;
683 reg = <0x00 0x040320000 0x00 0x400>;
686 #size-cells = <0>;
694 reg = <0x00 0x42040000 0x00 0x350>,
695 <0x00 0x42050000 0x00 0x350>,
696 <0x00 0x43000300 0x00 0x10>;
704 reg = <0x00 0x40800000 0x00 0x1000>;