Lines Matching +full:phy +full:- +full:am654 +full:- +full:serdes
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
20 cmn_refclk1: clock-cmnrefclk1 {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <0>;
29 compatible = "mmio-sram";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 atf-sram@0 {
40 scm_conf: scm-conf@100000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
43 #address-cells = <1>;
44 #size-cells = <1>;
47 serdes_ln_ctrl: mux-controller@4080 {
48 compatible = "reg-mux";
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
57 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
65 cpsw0_phy_gmii_sel: phy@4044 {
66 compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
67 ti,qsgmii-main-ports = <2>, <2>;
69 #phy-cells = <1>;
72 usb_serdes_mux: mux-controller@4000 {
73 compatible = "reg-mux";
75 #mux-control-cells = <1>;
76 mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */
80 ehrpwm_tbclk: clock-controller@4140 {
81 compatible = "ti,am654-ehrpwm-tbclk";
83 #clock-cells = <1>;
88 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
89 #pwm-cells = <3>;
91 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
93 clock-names = "tbclk", "fck";
98 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
99 #pwm-cells = <3>;
101 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
103 clock-names = "tbclk", "fck";
108 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
109 #pwm-cells = <3>;
111 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
113 clock-names = "tbclk", "fck";
118 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
119 #pwm-cells = <3>;
121 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
123 clock-names = "tbclk", "fck";
128 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
129 #pwm-cells = <3>;
131 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
133 clock-names = "tbclk", "fck";
138 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
139 #pwm-cells = <3>;
141 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
143 clock-names = "tbclk", "fck";
147 gic500: interrupt-controller@1800000 {
148 compatible = "arm,gic-v3";
149 #address-cells = <2>;
150 #size-cells = <2>;
152 #interrupt-cells = <3>;
153 interrupt-controller;
163 gic_its: msi-controller@1820000 {
164 compatible = "arm,gic-v3-its";
166 socionext,synquacer-pre-its = <0x1000000 0x400000>;
167 msi-controller;
168 #msi-cells = <1>;
172 main_gpio_intr: interrupt-controller@a00000 {
173 compatible = "ti,sci-intr";
175 ti,intr-trigger-type = <1>;
176 interrupt-controller;
177 interrupt-parent = <&gic500>;
178 #interrupt-cells = <1>;
180 ti,sci-dev-id = <131>;
181 ti,interrupt-ranges = <8 392 56>;
185 compatible = "simple-bus";
186 #address-cells = <2>;
187 #size-cells = <2>;
189 dma-coherent;
190 dma-ranges;
192 ti,sci-dev-id = <199>;
194 main_navss_intr: interrupt-controller@310e0000 {
195 compatible = "ti,sci-intr";
197 ti,intr-trigger-type = <4>;
198 interrupt-controller;
199 interrupt-parent = <&gic500>;
200 #interrupt-cells = <1>;
202 ti,sci-dev-id = <213>;
203 ti,interrupt-ranges = <0 64 64>,
208 main_udmass_inta: interrupt-controller@33d00000 {
209 compatible = "ti,sci-inta";
211 interrupt-controller;
212 interrupt-parent = <&main_navss_intr>;
213 msi-controller;
214 #interrupt-cells = <0>;
216 ti,sci-dev-id = <209>;
217 ti,interrupt-ranges = <0 0 256>;
221 compatible = "ti,am654-secure-proxy";
222 #mbox-cells = <1>;
223 reg-names = "target_data", "rt", "scfg";
227 interrupt-names = "rx_011";
232 compatible = "arm,smmu-v3";
234 interrupt-parent = <&gic500>;
237 interrupt-names = "eventq", "gerror";
238 #iommu-cells = <1>;
242 compatible = "ti,am654-hwspinlock";
244 #hwlock-cells = <1>;
248 compatible = "ti,am654-mailbox";
250 #mbox-cells = <1>;
251 ti,mbox-num-users = <4>;
252 ti,mbox-num-fifos = <16>;
253 interrupt-parent = <&main_navss_intr>;
258 compatible = "ti,am654-mailbox";
260 #mbox-cells = <1>;
261 ti,mbox-num-users = <4>;
262 ti,mbox-num-fifos = <16>;
263 interrupt-parent = <&main_navss_intr>;
268 compatible = "ti,am654-mailbox";
270 #mbox-cells = <1>;
271 ti,mbox-num-users = <4>;
272 ti,mbox-num-fifos = <16>;
273 interrupt-parent = <&main_navss_intr>;
278 compatible = "ti,am654-mailbox";
280 #mbox-cells = <1>;
281 ti,mbox-num-users = <4>;
282 ti,mbox-num-fifos = <16>;
283 interrupt-parent = <&main_navss_intr>;
288 compatible = "ti,am654-mailbox";
290 #mbox-cells = <1>;
291 ti,mbox-num-users = <4>;
292 ti,mbox-num-fifos = <16>;
293 interrupt-parent = <&main_navss_intr>;
298 compatible = "ti,am654-mailbox";
300 #mbox-cells = <1>;
301 ti,mbox-num-users = <4>;
302 ti,mbox-num-fifos = <16>;
303 interrupt-parent = <&main_navss_intr>;
308 compatible = "ti,am654-mailbox";
310 #mbox-cells = <1>;
311 ti,mbox-num-users = <4>;
312 ti,mbox-num-fifos = <16>;
313 interrupt-parent = <&main_navss_intr>;
318 compatible = "ti,am654-mailbox";
320 #mbox-cells = <1>;
321 ti,mbox-num-users = <4>;
322 ti,mbox-num-fifos = <16>;
323 interrupt-parent = <&main_navss_intr>;
328 compatible = "ti,am654-mailbox";
330 #mbox-cells = <1>;
331 ti,mbox-num-users = <4>;
332 ti,mbox-num-fifos = <16>;
333 interrupt-parent = <&main_navss_intr>;
338 compatible = "ti,am654-mailbox";
340 #mbox-cells = <1>;
341 ti,mbox-num-users = <4>;
342 ti,mbox-num-fifos = <16>;
343 interrupt-parent = <&main_navss_intr>;
348 compatible = "ti,am654-mailbox";
350 #mbox-cells = <1>;
351 ti,mbox-num-users = <4>;
352 ti,mbox-num-fifos = <16>;
353 interrupt-parent = <&main_navss_intr>;
358 compatible = "ti,am654-mailbox";
360 #mbox-cells = <1>;
361 ti,mbox-num-users = <4>;
362 ti,mbox-num-fifos = <16>;
363 interrupt-parent = <&main_navss_intr>;
368 compatible = "ti,am654-navss-ringacc";
374 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
375 ti,num-rings = <1024>;
376 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
378 ti,sci-dev-id = <211>;
379 msi-parent = <&main_udmass_inta>;
382 main_udmap: dma-controller@31150000 {
383 compatible = "ti,j721e-navss-main-udmap";
390 reg-names = "gcfg", "rchanrt", "tchanrt",
392 msi-parent = <&main_udmass_inta>;
393 #dma-cells = <1>;
396 ti,sci-dev-id = <212>;
399 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
402 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
405 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
409 compatible = "ti,j721e-cpts";
411 reg-names = "cpts";
413 clock-names = "cpts";
414 interrupts-extended = <&main_navss_intr 391>;
415 interrupt-names = "cpts";
416 ti,cpts-periodic-outputs = <6>;
417 ti,cpts-ext-ts-inputs = <8>;
422 compatible = "ti,j721e-cpswxg-nuss";
423 #address-cells = <2>;
424 #size-cells = <2>;
426 reg-names = "cpsw_nuss";
429 clock-names = "fck";
430 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
441 dma-names = "tx0", "tx1", "tx2", "tx3",
447 ethernet-ports {
448 #address-cells = <1>;
449 #size-cells = <0>;
452 ti,mac-only;
459 ti,mac-only;
466 ti,mac-only;
473 ti,mac-only;
480 ti,mac-only;
487 ti,mac-only;
494 ti,mac-only;
501 ti,mac-only;
508 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
510 #address-cells = <1>;
511 #size-cells = <0>;
513 clock-names = "fck";
519 compatible = "ti,j721e-cpts";
522 clock-names = "cpts";
523 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
524 interrupt-names = "cpts";
525 ti,cpts-ext-ts-inputs = <4>;
526 ti,cpts-periodic-outputs = <2>;
531 compatible = "ti,j721e-sa2ul";
533 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
534 #address-cells = <2>;
535 #size-cells = <2>;
540 dma-names = "tx", "rx1", "rx2";
543 compatible = "inside-secure,safexcel-eip76";
550 compatible = "pinctrl-single";
553 #pinctrl-cells = <1>;
554 pinctrl-single,register-width = <32>;
555 pinctrl-single,function-mask = <0xffffffff>;
560 compatible = "pinctrl-single";
562 #pinctrl-cells = <1>;
563 pinctrl-single,register-width = <32>;
564 pinctrl-single,function-mask = <0x00000007>;
569 compatible = "pinctrl-single";
571 #pinctrl-cells = <1>;
572 pinctrl-single,register-width = <32>;
573 pinctrl-single,function-mask = <0x0000001f>;
577 compatible = "ti,j721e-csi2rx-shim";
580 #address-cells = <2>;
581 #size-cells = <2>;
583 dma-names = "rx0";
584 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
587 cdns_csi2rx0: csi-bridge@4504000 {
588 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
592 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
595 phy-names = "dphy";
598 #address-cells = <1>;
599 #size-cells = <0>;
630 compatible = "ti,j721e-csi2rx-shim";
633 #address-cells = <2>;
634 #size-cells = <2>;
636 dma-names = "rx0";
637 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
640 cdns_csi2rx1: csi-bridge@4514000 {
641 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
645 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
648 phy-names = "dphy";
651 #address-cells = <1>;
652 #size-cells = <0>;
682 dphy0: phy@4580000 {
683 compatible = "cdns,dphy-rx";
685 #phy-cells = <0>;
686 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
690 dphy1: phy@4590000 {
691 compatible = "cdns,dphy-rx";
693 #phy-cells = <0>;
694 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
699 compatible = "ti,j721e-wiz-16g";
700 #address-cells = <1>;
701 #size-cells = <1>;
702 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
704 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
705 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
706 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
707 num-lanes = <2>;
708 #reset-cells = <1>;
711 wiz0_pll0_refclk: pll0-refclk {
713 #clock-cells = <0>;
714 assigned-clocks = <&wiz0_pll0_refclk>;
715 assigned-clock-parents = <&k3_clks 292 11>;
718 wiz0_pll1_refclk: pll1-refclk {
720 #clock-cells = <0>;
721 assigned-clocks = <&wiz0_pll1_refclk>;
722 assigned-clock-parents = <&k3_clks 292 0>;
725 wiz0_refclk_dig: refclk-dig {
727 #clock-cells = <0>;
728 assigned-clocks = <&wiz0_refclk_dig>;
729 assigned-clock-parents = <&k3_clks 292 11>;
732 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
734 #clock-cells = <0>;
737 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
739 #clock-cells = <0>;
742 serdes0: serdes@5000000 {
743 compatible = "ti,sierra-phy-t0";
744 reg-names = "serdes";
746 #address-cells = <1>;
747 #size-cells = <0>;
748 #clock-cells = <1>;
750 reset-names = "sierra_reset";
753 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
759 compatible = "ti,j721e-wiz-16g";
760 #address-cells = <1>;
761 #size-cells = <1>;
762 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
764 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
765 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
766 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
767 num-lanes = <2>;
768 #reset-cells = <1>;
771 wiz1_pll0_refclk: pll0-refclk {
773 #clock-cells = <0>;
774 assigned-clocks = <&wiz1_pll0_refclk>;
775 assigned-clock-parents = <&k3_clks 293 13>;
778 wiz1_pll1_refclk: pll1-refclk {
780 #clock-cells = <0>;
781 assigned-clocks = <&wiz1_pll1_refclk>;
782 assigned-clock-parents = <&k3_clks 293 0>;
785 wiz1_refclk_dig: refclk-dig {
787 #clock-cells = <0>;
788 assigned-clocks = <&wiz1_refclk_dig>;
789 assigned-clock-parents = <&k3_clks 293 13>;
792 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
794 #clock-cells = <0>;
797 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
799 #clock-cells = <0>;
802 serdes1: serdes@5010000 {
803 compatible = "ti,sierra-phy-t0";
804 reg-names = "serdes";
806 #address-cells = <1>;
807 #size-cells = <0>;
808 #clock-cells = <1>;
810 reset-names = "sierra_reset";
813 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
819 compatible = "ti,j721e-wiz-16g";
820 #address-cells = <1>;
821 #size-cells = <1>;
822 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
824 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
825 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
826 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
827 num-lanes = <2>;
828 #reset-cells = <1>;
831 wiz2_pll0_refclk: pll0-refclk {
833 #clock-cells = <0>;
834 assigned-clocks = <&wiz2_pll0_refclk>;
835 assigned-clock-parents = <&k3_clks 294 11>;
838 wiz2_pll1_refclk: pll1-refclk {
840 #clock-cells = <0>;
841 assigned-clocks = <&wiz2_pll1_refclk>;
842 assigned-clock-parents = <&k3_clks 294 0>;
845 wiz2_refclk_dig: refclk-dig {
847 #clock-cells = <0>;
848 assigned-clocks = <&wiz2_refclk_dig>;
849 assigned-clock-parents = <&k3_clks 294 11>;
852 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
854 #clock-cells = <0>;
857 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
859 #clock-cells = <0>;
862 serdes2: serdes@5020000 {
863 compatible = "ti,sierra-phy-t0";
864 reg-names = "serdes";
866 #address-cells = <1>;
867 #size-cells = <0>;
868 #clock-cells = <1>;
870 reset-names = "sierra_reset";
873 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
879 compatible = "ti,j721e-wiz-16g";
880 #address-cells = <1>;
881 #size-cells = <1>;
882 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
884 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
885 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
886 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
887 num-lanes = <2>;
888 #reset-cells = <1>;
891 wiz3_pll0_refclk: pll0-refclk {
893 #clock-cells = <0>;
894 assigned-clocks = <&wiz3_pll0_refclk>;
895 assigned-clock-parents = <&k3_clks 295 9>;
898 wiz3_pll1_refclk: pll1-refclk {
900 #clock-cells = <0>;
901 assigned-clocks = <&wiz3_pll1_refclk>;
902 assigned-clock-parents = <&k3_clks 295 0>;
905 wiz3_refclk_dig: refclk-dig {
907 #clock-cells = <0>;
908 assigned-clocks = <&wiz3_refclk_dig>;
909 assigned-clock-parents = <&k3_clks 295 9>;
912 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
914 #clock-cells = <0>;
917 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
919 #clock-cells = <0>;
922 serdes3: serdes@5030000 {
923 compatible = "ti,sierra-phy-t0";
924 reg-names = "serdes";
926 #address-cells = <1>;
927 #size-cells = <0>;
928 #clock-cells = <1>;
930 reset-names = "sierra_reset";
933 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
939 compatible = "ti,j721e-pcie-host";
944 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
945 interrupt-names = "link_state";
948 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
949 max-link-speed = <3>;
950 num-lanes = <2>;
951 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
953 clock-names = "fck";
954 #address-cells = <3>;
955 #size-cells = <2>;
956 bus-range = <0x0 0xff>;
957 vendor-id = <0x104c>;
958 device-id = <0xb00d>;
959 msi-map = <0x0 &gic_its 0x0 0x10000>;
960 dma-coherent;
963 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
968 compatible = "ti,j721e-pcie-host";
973 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
974 interrupt-names = "link_state";
977 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
978 max-link-speed = <3>;
979 num-lanes = <2>;
980 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
982 clock-names = "fck";
983 #address-cells = <3>;
984 #size-cells = <2>;
985 bus-range = <0x0 0xff>;
986 vendor-id = <0x104c>;
987 device-id = <0xb00d>;
988 msi-map = <0x0 &gic_its 0x10000 0x10000>;
989 dma-coherent;
992 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
997 compatible = "ti,j721e-pcie-host";
1002 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1003 interrupt-names = "link_state";
1006 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
1007 max-link-speed = <3>;
1008 num-lanes = <2>;
1009 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
1011 clock-names = "fck";
1012 #address-cells = <3>;
1013 #size-cells = <2>;
1014 bus-range = <0x0 0xff>;
1015 vendor-id = <0x104c>;
1016 device-id = <0xb00d>;
1017 msi-map = <0x0 &gic_its 0x20000 0x10000>;
1018 dma-coherent;
1021 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1026 compatible = "ti,j721e-pcie-host";
1031 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1032 interrupt-names = "link_state";
1035 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
1036 max-link-speed = <3>;
1037 num-lanes = <2>;
1038 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
1040 clock-names = "fck";
1041 #address-cells = <3>;
1042 #size-cells = <2>;
1043 bus-range = <0x0 0xff>;
1044 vendor-id = <0x104c>;
1045 device-id = <0xb00d>;
1046 msi-map = <0x0 &gic_its 0x30000 0x10000>;
1047 dma-coherent;
1050 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1055 compatible = "ti,am64-wiz-10g";
1056 #address-cells = <1>;
1057 #size-cells = <1>;
1058 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
1060 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1061 assigned-clocks = <&k3_clks 297 9>;
1062 assigned-clock-parents = <&k3_clks 297 10>;
1063 assigned-clock-rates = <19200000>;
1064 num-lanes = <4>;
1065 #reset-cells = <1>;
1066 #clock-cells = <1>;
1070 serdes4: serdes@5050000 {
1072 * Note: we also map DPTX PHY registers as the Torrent
1075 compatible = "ti,j721e-serdes-10g";
1077 <0x0a030a00 0x40>; /* DPTX PHY */
1078 reg-names = "torrent_phy", "dptx_phy";
1081 reset-names = "torrent_reset";
1083 clock-names = "refclk";
1084 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
1087 assigned-clock-parents = <&k3_clks 297 9>,
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1096 compatible = "ti,am654-timer";
1100 clock-names = "fck";
1101 assigned-clocks = <&k3_clks 49 1>;
1102 assigned-clock-parents = <&k3_clks 49 2>;
1103 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1104 ti,timer-pwm;
1108 compatible = "ti,am654-timer";
1112 clock-names = "fck";
1113 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
1114 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
1115 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1116 ti,timer-pwm;
1120 compatible = "ti,am654-timer";
1124 clock-names = "fck";
1125 assigned-clocks = <&k3_clks 51 1>;
1126 assigned-clock-parents = <&k3_clks 51 2>;
1127 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
1128 ti,timer-pwm;
1132 compatible = "ti,am654-timer";
1136 clock-names = "fck";
1137 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
1138 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
1139 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1140 ti,timer-pwm;
1144 compatible = "ti,am654-timer";
1148 clock-names = "fck";
1149 assigned-clocks = <&k3_clks 53 1>;
1150 assigned-clock-parents = <&k3_clks 53 2>;
1151 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1152 ti,timer-pwm;
1156 compatible = "ti,am654-timer";
1160 clock-names = "fck";
1161 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
1162 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
1163 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1164 ti,timer-pwm;
1168 compatible = "ti,am654-timer";
1172 clock-names = "fck";
1173 assigned-clocks = <&k3_clks 55 1>;
1174 assigned-clock-parents = <&k3_clks 55 2>;
1175 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1176 ti,timer-pwm;
1180 compatible = "ti,am654-timer";
1184 clock-names = "fck";
1185 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
1186 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
1187 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1188 ti,timer-pwm;
1192 compatible = "ti,am654-timer";
1196 clock-names = "fck";
1197 assigned-clocks = <&k3_clks 58 1>;
1198 assigned-clock-parents = <&k3_clks 58 2>;
1199 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1200 ti,timer-pwm;
1204 compatible = "ti,am654-timer";
1208 clock-names = "fck";
1209 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
1210 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
1211 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1212 ti,timer-pwm;
1216 compatible = "ti,am654-timer";
1220 clock-names = "fck";
1221 assigned-clocks = <&k3_clks 60 1>;
1222 assigned-clock-parents = <&k3_clks 60 2>;
1223 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1224 ti,timer-pwm;
1228 compatible = "ti,am654-timer";
1232 clock-names = "fck";
1233 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
1234 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
1235 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1236 ti,timer-pwm;
1240 compatible = "ti,am654-timer";
1244 clock-names = "fck";
1245 assigned-clocks = <&k3_clks 63 1>;
1246 assigned-clock-parents = <&k3_clks 63 2>;
1247 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1248 ti,timer-pwm;
1252 compatible = "ti,am654-timer";
1256 clock-names = "fck";
1257 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
1258 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
1259 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1260 ti,timer-pwm;
1264 compatible = "ti,am654-timer";
1268 clock-names = "fck";
1269 assigned-clocks = <&k3_clks 65 1>;
1270 assigned-clock-parents = <&k3_clks 65 2>;
1271 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1272 ti,timer-pwm;
1276 compatible = "ti,am654-timer";
1280 clock-names = "fck";
1281 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
1282 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
1283 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1284 ti,timer-pwm;
1288 compatible = "ti,am654-timer";
1292 clock-names = "fck";
1293 assigned-clocks = <&k3_clks 67 1>;
1294 assigned-clock-parents = <&k3_clks 67 2>;
1295 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1296 ti,timer-pwm;
1300 compatible = "ti,am654-timer";
1304 clock-names = "fck";
1305 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
1306 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
1307 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1308 ti,timer-pwm;
1312 compatible = "ti,am654-timer";
1316 clock-names = "fck";
1317 assigned-clocks = <&k3_clks 69 1>;
1318 assigned-clock-parents = <&k3_clks 69 2>;
1319 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1320 ti,timer-pwm;
1324 compatible = "ti,am654-timer";
1328 clock-names = "fck";
1329 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
1330 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
1331 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1332 ti,timer-pwm;
1336 compatible = "ti,j721e-uart", "ti,am654-uart";
1339 clock-frequency = <48000000>;
1340 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
1342 clock-names = "fclk";
1347 compatible = "ti,j721e-uart", "ti,am654-uart";
1350 clock-frequency = <48000000>;
1351 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1353 clock-names = "fclk";
1358 compatible = "ti,j721e-uart", "ti,am654-uart";
1361 clock-frequency = <48000000>;
1362 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
1364 clock-names = "fclk";
1369 compatible = "ti,j721e-uart", "ti,am654-uart";
1372 clock-frequency = <48000000>;
1373 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
1375 clock-names = "fclk";
1380 compatible = "ti,j721e-uart", "ti,am654-uart";
1383 clock-frequency = <48000000>;
1384 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
1386 clock-names = "fclk";
1391 compatible = "ti,j721e-uart", "ti,am654-uart";
1394 clock-frequency = <48000000>;
1395 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
1397 clock-names = "fclk";
1402 compatible = "ti,j721e-uart", "ti,am654-uart";
1405 clock-frequency = <48000000>;
1406 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
1408 clock-names = "fclk";
1413 compatible = "ti,j721e-uart", "ti,am654-uart";
1416 clock-frequency = <48000000>;
1417 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
1419 clock-names = "fclk";
1424 compatible = "ti,j721e-uart", "ti,am654-uart";
1427 clock-frequency = <48000000>;
1428 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
1430 clock-names = "fclk";
1435 compatible = "ti,j721e-uart", "ti,am654-uart";
1438 clock-frequency = <48000000>;
1439 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1441 clock-names = "fclk";
1446 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1448 gpio-controller;
1449 #gpio-cells = <2>;
1450 interrupt-parent = <&main_gpio_intr>;
1453 interrupt-controller;
1454 #interrupt-cells = <2>;
1456 ti,davinci-gpio-unbanked = <0>;
1457 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
1459 clock-names = "gpio";
1464 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1466 gpio-controller;
1467 #gpio-cells = <2>;
1468 interrupt-parent = <&main_gpio_intr>;
1470 interrupt-controller;
1471 #interrupt-cells = <2>;
1473 ti,davinci-gpio-unbanked = <0>;
1474 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
1476 clock-names = "gpio";
1481 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1483 gpio-controller;
1484 #gpio-cells = <2>;
1485 interrupt-parent = <&main_gpio_intr>;
1488 interrupt-controller;
1489 #interrupt-cells = <2>;
1491 ti,davinci-gpio-unbanked = <0>;
1492 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
1494 clock-names = "gpio";
1499 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1501 gpio-controller;
1502 #gpio-cells = <2>;
1503 interrupt-parent = <&main_gpio_intr>;
1505 interrupt-controller;
1506 #interrupt-cells = <2>;
1508 ti,davinci-gpio-unbanked = <0>;
1509 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1511 clock-names = "gpio";
1516 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1518 gpio-controller;
1519 #gpio-cells = <2>;
1520 interrupt-parent = <&main_gpio_intr>;
1523 interrupt-controller;
1524 #interrupt-cells = <2>;
1526 ti,davinci-gpio-unbanked = <0>;
1527 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1529 clock-names = "gpio";
1534 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1536 gpio-controller;
1537 #gpio-cells = <2>;
1538 interrupt-parent = <&main_gpio_intr>;
1540 interrupt-controller;
1541 #interrupt-cells = <2>;
1543 ti,davinci-gpio-unbanked = <0>;
1544 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1546 clock-names = "gpio";
1551 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1553 gpio-controller;
1554 #gpio-cells = <2>;
1555 interrupt-parent = <&main_gpio_intr>;
1558 interrupt-controller;
1559 #interrupt-cells = <2>;
1561 ti,davinci-gpio-unbanked = <0>;
1562 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1564 clock-names = "gpio";
1569 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1571 gpio-controller;
1572 #gpio-cells = <2>;
1573 interrupt-parent = <&main_gpio_intr>;
1575 interrupt-controller;
1576 #interrupt-cells = <2>;
1578 ti,davinci-gpio-unbanked = <0>;
1579 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1581 clock-names = "gpio";
1586 compatible = "ti,j721e-sdhci-8bit";
1589 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1590 clock-names = "clk_ahb", "clk_xin";
1592 assigned-clocks = <&k3_clks 91 1>;
1593 assigned-clock-parents = <&k3_clks 91 2>;
1594 bus-width = <8>;
1595 mmc-hs200-1_8v;
1596 mmc-ddr-1_8v;
1597 ti,otap-del-sel-legacy = <0x0>;
1598 ti,otap-del-sel-mmc-hs = <0x0>;
1599 ti,otap-del-sel-ddr52 = <0x5>;
1600 ti,otap-del-sel-hs200 = <0x6>;
1601 ti,otap-del-sel-hs400 = <0x0>;
1602 ti,itap-del-sel-legacy = <0x10>;
1603 ti,itap-del-sel-mmc-hs = <0xa>;
1604 ti,itap-del-sel-ddr52 = <0x3>;
1605 ti,trm-icp = <0x8>;
1606 dma-coherent;
1611 compatible = "ti,j721e-sdhci-4bit";
1614 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1615 clock-names = "clk_ahb", "clk_xin";
1617 assigned-clocks = <&k3_clks 92 0>;
1618 assigned-clock-parents = <&k3_clks 92 1>;
1619 ti,otap-del-sel-legacy = <0x0>;
1620 ti,otap-del-sel-sd-hs = <0x0>;
1621 ti,otap-del-sel-sdr12 = <0xf>;
1622 ti,otap-del-sel-sdr25 = <0xf>;
1623 ti,otap-del-sel-sdr50 = <0xc>;
1624 ti,otap-del-sel-ddr50 = <0xc>;
1625 ti,otap-del-sel-sdr104 = <0x5>;
1626 ti,itap-del-sel-legacy = <0x0>;
1627 ti,itap-del-sel-sd-hs = <0x0>;
1628 ti,itap-del-sel-sdr12 = <0x0>;
1629 ti,itap-del-sel-sdr25 = <0x0>;
1630 ti,itap-del-sel-ddr50 = <0x2>;
1631 ti,trm-icp = <0x8>;
1632 ti,clkbuf-sel = <0x7>;
1633 dma-coherent;
1634 sdhci-caps-mask = <0x2 0x0>;
1639 compatible = "ti,j721e-sdhci-4bit";
1642 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1643 clock-names = "clk_ahb", "clk_xin";
1645 assigned-clocks = <&k3_clks 93 0>;
1646 assigned-clock-parents = <&k3_clks 93 1>;
1647 ti,otap-del-sel-legacy = <0x0>;
1648 ti,otap-del-sel-sd-hs = <0x0>;
1649 ti,otap-del-sel-sdr12 = <0xf>;
1650 ti,otap-del-sel-sdr25 = <0xf>;
1651 ti,otap-del-sel-sdr50 = <0xc>;
1652 ti,otap-del-sel-ddr50 = <0xc>;
1653 ti,otap-del-sel-sdr104 = <0x5>;
1654 ti,itap-del-sel-legacy = <0x0>;
1655 ti,itap-del-sel-sd-hs = <0x0>;
1656 ti,itap-del-sel-sdr12 = <0x0>;
1657 ti,itap-del-sel-sdr25 = <0x0>;
1658 ti,itap-del-sel-ddr50 = <0x2>;
1659 ti,trm-icp = <0x8>;
1660 ti,clkbuf-sel = <0x7>;
1661 dma-coherent;
1662 sdhci-caps-mask = <0x2 0x0>;
1666 usbss0: cdns-usb@4104000 {
1667 compatible = "ti,j721e-usb";
1669 dma-coherent;
1670 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1672 clock-names = "ref", "lpm";
1673 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
1674 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1675 #address-cells = <2>;
1676 #size-cells = <2>;
1684 reg-names = "otg", "xhci", "dev";
1688 interrupt-names = "host",
1691 maximum-speed = "super-speed";
1696 usbss1: cdns-usb@4114000 {
1697 compatible = "ti,j721e-usb";
1699 dma-coherent;
1700 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1702 clock-names = "ref", "lpm";
1703 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
1704 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1705 #address-cells = <2>;
1706 #size-cells = <2>;
1714 reg-names = "otg", "xhci", "dev";
1718 interrupt-names = "host",
1721 maximum-speed = "super-speed";
1727 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1730 #address-cells = <1>;
1731 #size-cells = <0>;
1732 clock-names = "fck";
1734 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1739 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1742 #address-cells = <1>;
1743 #size-cells = <0>;
1744 clock-names = "fck";
1746 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1751 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1754 #address-cells = <1>;
1755 #size-cells = <0>;
1756 clock-names = "fck";
1758 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1763 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1766 #address-cells = <1>;
1767 #size-cells = <0>;
1768 clock-names = "fck";
1770 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1775 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1778 #address-cells = <1>;
1779 #size-cells = <0>;
1780 clock-names = "fck";
1782 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1787 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1790 #address-cells = <1>;
1791 #size-cells = <0>;
1792 clock-names = "fck";
1794 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1799 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1802 #address-cells = <1>;
1803 #size-cells = <0>;
1804 clock-names = "fck";
1806 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1810 ufs_wrapper: ufs-wrapper@4e80000 {
1811 compatible = "ti,j721e-ufs";
1813 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1815 assigned-clocks = <&k3_clks 277 1>;
1816 assigned-clock-parents = <&k3_clks 277 4>;
1818 #address-cells = <2>;
1819 #size-cells = <2>;
1822 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1825 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1827 clock-names = "core_clk", "phy_clk", "ref_clk";
1828 dma-coherent;
1832 mhdp: dp-bridge@a000000 {
1833 compatible = "ti,j721e-mhdp8546";
1835 * Note: we do not map DPTX PHY area, as that is handled by
1836 * the PHY driver.
1840 reg-names = "mhdptx", "j721e-intg";
1844 interrupt-parent = <&gic500>;
1847 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1850 #address-cells = <1>;
1851 #size-cells = <0>;
1864 compatible = "ti,j721e-dss";
1887 reg-names = "common_m", "common_s0",
1899 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1901 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1907 interrupt-names = "common_m",
1917 compatible = "ti,am33xx-mcasp-audio";
1920 reg-names = "mpu","dat";
1923 interrupt-names = "tx", "rx";
1926 dma-names = "tx", "rx";
1929 clock-names = "fck";
1930 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1935 compatible = "ti,am33xx-mcasp-audio";
1938 reg-names = "mpu","dat";
1941 interrupt-names = "tx", "rx";
1944 dma-names = "tx", "rx";
1947 clock-names = "fck";
1948 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1953 compatible = "ti,am33xx-mcasp-audio";
1956 reg-names = "mpu","dat";
1959 interrupt-names = "tx", "rx";
1962 dma-names = "tx", "rx";
1965 clock-names = "fck";
1966 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1971 compatible = "ti,am33xx-mcasp-audio";
1974 reg-names = "mpu","dat";
1977 interrupt-names = "tx", "rx";
1980 dma-names = "tx", "rx";
1983 clock-names = "fck";
1984 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1989 compatible = "ti,am33xx-mcasp-audio";
1992 reg-names = "mpu","dat";
1995 interrupt-names = "tx", "rx";
1998 dma-names = "tx", "rx";
2001 clock-names = "fck";
2002 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
2007 compatible = "ti,am33xx-mcasp-audio";
2010 reg-names = "mpu","dat";
2013 interrupt-names = "tx", "rx";
2016 dma-names = "tx", "rx";
2019 clock-names = "fck";
2020 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
2025 compatible = "ti,am33xx-mcasp-audio";
2028 reg-names = "mpu","dat";
2031 interrupt-names = "tx", "rx";
2034 dma-names = "tx", "rx";
2037 clock-names = "fck";
2038 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
2043 compatible = "ti,am33xx-mcasp-audio";
2046 reg-names = "mpu","dat";
2049 interrupt-names = "tx", "rx";
2052 dma-names = "tx", "rx";
2055 clock-names = "fck";
2056 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
2061 compatible = "ti,am33xx-mcasp-audio";
2064 reg-names = "mpu","dat";
2067 interrupt-names = "tx", "rx";
2070 dma-names = "tx", "rx";
2073 clock-names = "fck";
2074 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
2079 compatible = "ti,am33xx-mcasp-audio";
2082 reg-names = "mpu","dat";
2085 interrupt-names = "tx", "rx";
2088 dma-names = "tx", "rx";
2091 clock-names = "fck";
2092 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
2097 compatible = "ti,am33xx-mcasp-audio";
2100 reg-names = "mpu","dat";
2103 interrupt-names = "tx", "rx";
2106 dma-names = "tx", "rx";
2109 clock-names = "fck";
2110 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
2115 compatible = "ti,am33xx-mcasp-audio";
2118 reg-names = "mpu","dat";
2121 interrupt-names = "tx", "rx";
2124 dma-names = "tx", "rx";
2127 clock-names = "fck";
2128 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
2133 compatible = "ti,j7-rti-wdt";
2136 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
2137 assigned-clocks = <&k3_clks 252 1>;
2138 assigned-clock-parents = <&k3_clks 252 5>;
2142 compatible = "ti,j7-rti-wdt";
2145 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
2146 assigned-clocks = <&k3_clks 253 1>;
2147 assigned-clock-parents = <&k3_clks 253 5>;
2151 compatible = "ti,j721e-r5fss";
2152 ti,cluster-mode = <1>;
2153 #address-cells = <1>;
2154 #size-cells = <1>;
2157 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
2160 compatible = "ti,j721e-r5f";
2163 reg-names = "atcm", "btcm";
2165 ti,sci-dev-id = <245>;
2166 ti,sci-proc-ids = <0x06 0xff>;
2168 firmware-name = "j7-main-r5f0_0-fw";
2169 ti,atcm-enable = <1>;
2170 ti,btcm-enable = <1>;
2175 compatible = "ti,j721e-r5f";
2178 reg-names = "atcm", "btcm";
2180 ti,sci-dev-id = <246>;
2181 ti,sci-proc-ids = <0x07 0xff>;
2183 firmware-name = "j7-main-r5f0_1-fw";
2184 ti,atcm-enable = <1>;
2185 ti,btcm-enable = <1>;
2191 compatible = "ti,j721e-r5fss";
2192 ti,cluster-mode = <1>;
2193 #address-cells = <1>;
2194 #size-cells = <1>;
2197 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
2200 compatible = "ti,j721e-r5f";
2203 reg-names = "atcm", "btcm";
2205 ti,sci-dev-id = <247>;
2206 ti,sci-proc-ids = <0x08 0xff>;
2208 firmware-name = "j7-main-r5f1_0-fw";
2209 ti,atcm-enable = <1>;
2210 ti,btcm-enable = <1>;
2215 compatible = "ti,j721e-r5f";
2218 reg-names = "atcm", "btcm";
2220 ti,sci-dev-id = <248>;
2221 ti,sci-proc-ids = <0x09 0xff>;
2223 firmware-name = "j7-main-r5f1_1-fw";
2224 ti,atcm-enable = <1>;
2225 ti,btcm-enable = <1>;
2231 compatible = "ti,j721e-c66-dsp";
2235 reg-names = "l2sram", "l1pram", "l1dram";
2237 ti,sci-dev-id = <142>;
2238 ti,sci-proc-ids = <0x03 0xff>;
2240 firmware-name = "j7-c66_0-fw";
2245 compatible = "ti,j721e-c66-dsp";
2249 reg-names = "l2sram", "l1pram", "l1dram";
2251 ti,sci-dev-id = <143>;
2252 ti,sci-proc-ids = <0x04 0xff>;
2254 firmware-name = "j7-c66_1-fw";
2259 compatible = "ti,j721e-c71-dsp";
2262 reg-names = "l2sram", "l1dram";
2264 ti,sci-dev-id = <15>;
2265 ti,sci-proc-ids = <0x30 0xff>;
2267 firmware-name = "j7-c71_0-fw";
2272 compatible = "ti,j721e-icssg";
2274 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
2275 #address-cells = <1>;
2276 #size-cells = <1>;
2283 reg-names = "dram0", "dram1",
2288 compatible = "ti,pruss-cfg", "syscon";
2290 #address-cells = <1>;
2291 #size-cells = <1>;
2295 #address-cells = <1>;
2296 #size-cells = <0>;
2298 icssg0_coreclk_mux: coreclk-mux@3c {
2300 #clock-cells = <0>;
2303 assigned-clocks = <&icssg0_coreclk_mux>;
2304 assigned-clock-parents = <&k3_clks 119 1>;
2307 icssg0_iepclk_mux: iepclk-mux@30 {
2309 #clock-cells = <0>;
2312 assigned-clocks = <&icssg0_iepclk_mux>;
2313 assigned-clock-parents = <&icssg0_coreclk_mux>;
2318 icssg0_mii_rt: mii-rt@32000 {
2319 compatible = "ti,pruss-mii", "syscon";
2323 icssg0_mii_g_rt: mii-g-rt@33000 {
2324 compatible = "ti,pruss-mii-g", "syscon";
2328 icssg0_intc: interrupt-controller@20000 {
2329 compatible = "ti,icssg-intc";
2331 interrupt-controller;
2332 #interrupt-cells = <3>;
2341 interrupt-names = "host_intr0", "host_intr1",
2348 compatible = "ti,j721e-pru";
2352 reg-names = "iram", "control", "debug";
2353 firmware-name = "j7-pru0_0-fw";
2357 compatible = "ti,j721e-rtu";
2361 reg-names = "iram", "control", "debug";
2362 firmware-name = "j7-rtu0_0-fw";
2366 compatible = "ti,j721e-tx-pru";
2370 reg-names = "iram", "control", "debug";
2371 firmware-name = "j7-txpru0_0-fw";
2375 compatible = "ti,j721e-pru";
2379 reg-names = "iram", "control", "debug";
2380 firmware-name = "j7-pru0_1-fw";
2384 compatible = "ti,j721e-rtu";
2388 reg-names = "iram", "control", "debug";
2389 firmware-name = "j7-rtu0_1-fw";
2393 compatible = "ti,j721e-tx-pru";
2397 reg-names = "iram", "control", "debug";
2398 firmware-name = "j7-txpru0_1-fw";
2405 clock-names = "fck";
2406 #address-cells = <1>;
2407 #size-cells = <0>;
2414 compatible = "ti,j721e-icssg";
2416 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
2417 #address-cells = <1>;
2418 #size-cells = <1>;
2425 reg-names = "dram0", "dram1",
2430 compatible = "ti,pruss-cfg", "syscon";
2432 #address-cells = <1>;
2433 #size-cells = <1>;
2437 #address-cells = <1>;
2438 #size-cells = <0>;
2440 icssg1_coreclk_mux: coreclk-mux@3c {
2442 #clock-cells = <0>;
2445 assigned-clocks = <&icssg1_coreclk_mux>;
2446 assigned-clock-parents = <&k3_clks 120 4>;
2449 icssg1_iepclk_mux: iepclk-mux@30 {
2451 #clock-cells = <0>;
2454 assigned-clocks = <&icssg1_iepclk_mux>;
2455 assigned-clock-parents = <&icssg1_coreclk_mux>;
2460 icssg1_mii_rt: mii-rt@32000 {
2461 compatible = "ti,pruss-mii", "syscon";
2465 icssg1_mii_g_rt: mii-g-rt@33000 {
2466 compatible = "ti,pruss-mii-g", "syscon";
2470 icssg1_intc: interrupt-controller@20000 {
2471 compatible = "ti,icssg-intc";
2473 interrupt-controller;
2474 #interrupt-cells = <3>;
2483 interrupt-names = "host_intr0", "host_intr1",
2490 compatible = "ti,j721e-pru";
2494 reg-names = "iram", "control", "debug";
2495 firmware-name = "j7-pru1_0-fw";
2499 compatible = "ti,j721e-rtu";
2503 reg-names = "iram", "control", "debug";
2504 firmware-name = "j7-rtu1_0-fw";
2508 compatible = "ti,j721e-tx-pru";
2512 reg-names = "iram", "control", "debug";
2513 firmware-name = "j7-txpru1_0-fw";
2517 compatible = "ti,j721e-pru";
2521 reg-names = "iram", "control", "debug";
2522 firmware-name = "j7-pru1_1-fw";
2526 compatible = "ti,j721e-rtu";
2530 reg-names = "iram", "control", "debug";
2531 firmware-name = "j7-rtu1_1-fw";
2535 compatible = "ti,j721e-tx-pru";
2539 reg-names = "iram", "control", "debug";
2540 firmware-name = "j7-txpru1_1-fw";
2547 clock-names = "fck";
2548 #address-cells = <1>;
2549 #size-cells = <0>;
2559 reg-names = "m_can", "message_ram";
2560 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
2562 clock-names = "hclk", "cclk";
2565 interrupt-names = "int0", "int1";
2566 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2574 reg-names = "m_can", "message_ram";
2575 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
2577 clock-names = "hclk", "cclk";
2580 interrupt-names = "int0", "int1";
2581 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2589 reg-names = "m_can", "message_ram";
2590 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
2592 clock-names = "hclk", "cclk";
2595 interrupt-names = "int0", "int1";
2596 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2604 reg-names = "m_can", "message_ram";
2605 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
2607 clock-names = "hclk", "cclk";
2610 interrupt-names = "int0", "int1";
2611 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2619 reg-names = "m_can", "message_ram";
2620 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
2622 clock-names = "hclk", "cclk";
2625 interrupt-names = "int0", "int1";
2626 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2634 reg-names = "m_can", "message_ram";
2635 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
2637 clock-names = "hclk", "cclk";
2640 interrupt-names = "int0", "int1";
2641 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2649 reg-names = "m_can", "message_ram";
2650 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
2652 clock-names = "hclk", "cclk";
2655 interrupt-names = "int0", "int1";
2656 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2664 reg-names = "m_can", "message_ram";
2665 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
2667 clock-names = "hclk", "cclk";
2670 interrupt-names = "int0", "int1";
2671 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2679 reg-names = "m_can", "message_ram";
2680 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
2682 clock-names = "hclk", "cclk";
2685 interrupt-names = "int0", "int1";
2686 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2694 reg-names = "m_can", "message_ram";
2695 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
2697 clock-names = "hclk", "cclk";
2700 interrupt-names = "int0", "int1";
2701 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2709 reg-names = "m_can", "message_ram";
2710 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
2712 clock-names = "hclk", "cclk";
2715 interrupt-names = "int0", "int1";
2716 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2724 reg-names = "m_can", "message_ram";
2725 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
2727 clock-names = "hclk", "cclk";
2730 interrupt-names = "int0", "int1";
2731 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2739 reg-names = "m_can", "message_ram";
2740 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
2742 clock-names = "hclk", "cclk";
2745 interrupt-names = "int0", "int1";
2746 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2754 reg-names = "m_can", "message_ram";
2755 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
2757 clock-names = "hclk", "cclk";
2760 interrupt-names = "int0", "int1";
2761 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2766 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2769 #address-cells = <1>;
2770 #size-cells = <0>;
2771 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
2777 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2780 #address-cells = <1>;
2781 #size-cells = <0>;
2782 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
2788 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2791 #address-cells = <1>;
2792 #size-cells = <0>;
2793 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
2799 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2802 #address-cells = <1>;
2803 #size-cells = <0>;
2804 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
2810 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2813 #address-cells = <1>;
2814 #size-cells = <0>;
2815 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
2821 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2824 #address-cells = <1>;
2825 #size-cells = <0>;
2826 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
2832 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2835 #address-cells = <1>;
2836 #size-cells = <0>;
2837 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
2843 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2846 #address-cells = <1>;
2847 #size-cells = <0>;
2848 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
2854 compatible = "ti,j721e-esm";
2856 ti,esm-pins = <344>, <345>;