Lines Matching +full:keystone +full:- +full:dsp +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
20 cmn_refclk1: clock-cmnrefclk1 {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <0>;
29 compatible = "mmio-sram";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 atf-sram@0 {
40 scm_conf: scm-conf@100000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
43 #address-cells = <1>;
44 #size-cells = <1>;
47 pcie0_ctrl: pcie-ctrl@4070 {
48 compatible = "ti,j784s4-pcie-ctrl", "syscon";
52 pcie1_ctrl: pcie-ctrl@4074 {
53 compatible = "ti,j784s4-pcie-ctrl", "syscon";
57 pcie2_ctrl: pcie-ctrl@4078 {
58 compatible = "ti,j784s4-pcie-ctrl", "syscon";
62 pcie3_ctrl: pcie-ctrl@407c {
63 compatible = "ti,j784s4-pcie-ctrl", "syscon";
67 serdes_ln_ctrl: mux-controller@4080 {
68 compatible = "reg-mux";
70 #mux-control-cells = <1>;
71 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
77 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
86 compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
87 ti,qsgmii-main-ports = <2>, <2>;
89 #phy-cells = <1>;
92 usb_serdes_mux: mux-controller@4000 {
93 compatible = "reg-mux";
95 #mux-control-cells = <1>;
96 mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */
100 ehrpwm_tbclk: clock-controller@4140 {
101 compatible = "ti,am654-ehrpwm-tbclk";
103 #clock-cells = <1>;
108 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
109 #pwm-cells = <3>;
111 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
113 clock-names = "tbclk", "fck";
118 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
119 #pwm-cells = <3>;
121 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
123 clock-names = "tbclk", "fck";
128 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
129 #pwm-cells = <3>;
131 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
133 clock-names = "tbclk", "fck";
138 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
139 #pwm-cells = <3>;
141 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
143 clock-names = "tbclk", "fck";
148 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
149 #pwm-cells = <3>;
151 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
153 clock-names = "tbclk", "fck";
158 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
159 #pwm-cells = <3>;
161 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
163 clock-names = "tbclk", "fck";
167 gic500: interrupt-controller@1800000 {
168 compatible = "arm,gic-v3";
169 #address-cells = <2>;
170 #size-cells = <2>;
172 #interrupt-cells = <3>;
173 interrupt-controller;
183 gic_its: msi-controller@1820000 {
184 compatible = "arm,gic-v3-its";
186 socionext,synquacer-pre-its = <0x1000000 0x400000>;
187 msi-controller;
188 #msi-cells = <1>;
192 main_gpio_intr: interrupt-controller@a00000 {
193 compatible = "ti,sci-intr";
195 ti,intr-trigger-type = <1>;
196 interrupt-controller;
197 interrupt-parent = <&gic500>;
198 #interrupt-cells = <1>;
200 ti,sci-dev-id = <131>;
201 ti,interrupt-ranges = <8 392 56>;
205 compatible = "simple-bus";
206 #address-cells = <2>;
207 #size-cells = <2>;
209 dma-coherent;
210 dma-ranges;
212 ti,sci-dev-id = <199>;
214 main_navss_intr: interrupt-controller@310e0000 {
215 compatible = "ti,sci-intr";
217 ti,intr-trigger-type = <4>;
218 interrupt-controller;
219 interrupt-parent = <&gic500>;
220 #interrupt-cells = <1>;
222 ti,sci-dev-id = <213>;
223 ti,interrupt-ranges = <0 64 64>,
228 main_udmass_inta: interrupt-controller@33d00000 {
229 compatible = "ti,sci-inta";
231 interrupt-controller;
232 interrupt-parent = <&main_navss_intr>;
233 msi-controller;
234 #interrupt-cells = <0>;
236 ti,sci-dev-id = <209>;
237 ti,interrupt-ranges = <0 0 256>;
241 compatible = "ti,am654-secure-proxy";
242 #mbox-cells = <1>;
243 reg-names = "target_data", "rt", "scfg";
247 interrupt-names = "rx_011";
249 bootph-all;
253 compatible = "arm,smmu-v3";
255 interrupt-parent = <&gic500>;
258 interrupt-names = "eventq", "gerror";
259 #iommu-cells = <1>;
263 compatible = "ti,am654-hwspinlock";
265 #hwlock-cells = <1>;
269 compatible = "ti,am654-mailbox";
271 #mbox-cells = <1>;
272 ti,mbox-num-users = <4>;
273 ti,mbox-num-fifos = <16>;
274 interrupt-parent = <&main_navss_intr>;
279 compatible = "ti,am654-mailbox";
281 #mbox-cells = <1>;
282 ti,mbox-num-users = <4>;
283 ti,mbox-num-fifos = <16>;
284 interrupt-parent = <&main_navss_intr>;
289 compatible = "ti,am654-mailbox";
291 #mbox-cells = <1>;
292 ti,mbox-num-users = <4>;
293 ti,mbox-num-fifos = <16>;
294 interrupt-parent = <&main_navss_intr>;
299 compatible = "ti,am654-mailbox";
301 #mbox-cells = <1>;
302 ti,mbox-num-users = <4>;
303 ti,mbox-num-fifos = <16>;
304 interrupt-parent = <&main_navss_intr>;
309 compatible = "ti,am654-mailbox";
311 #mbox-cells = <1>;
312 ti,mbox-num-users = <4>;
313 ti,mbox-num-fifos = <16>;
314 interrupt-parent = <&main_navss_intr>;
319 compatible = "ti,am654-mailbox";
321 #mbox-cells = <1>;
322 ti,mbox-num-users = <4>;
323 ti,mbox-num-fifos = <16>;
324 interrupt-parent = <&main_navss_intr>;
329 compatible = "ti,am654-mailbox";
331 #mbox-cells = <1>;
332 ti,mbox-num-users = <4>;
333 ti,mbox-num-fifos = <16>;
334 interrupt-parent = <&main_navss_intr>;
339 compatible = "ti,am654-mailbox";
341 #mbox-cells = <1>;
342 ti,mbox-num-users = <4>;
343 ti,mbox-num-fifos = <16>;
344 interrupt-parent = <&main_navss_intr>;
349 compatible = "ti,am654-mailbox";
351 #mbox-cells = <1>;
352 ti,mbox-num-users = <4>;
353 ti,mbox-num-fifos = <16>;
354 interrupt-parent = <&main_navss_intr>;
359 compatible = "ti,am654-mailbox";
361 #mbox-cells = <1>;
362 ti,mbox-num-users = <4>;
363 ti,mbox-num-fifos = <16>;
364 interrupt-parent = <&main_navss_intr>;
369 compatible = "ti,am654-mailbox";
371 #mbox-cells = <1>;
372 ti,mbox-num-users = <4>;
373 ti,mbox-num-fifos = <16>;
374 interrupt-parent = <&main_navss_intr>;
379 compatible = "ti,am654-mailbox";
381 #mbox-cells = <1>;
382 ti,mbox-num-users = <4>;
383 ti,mbox-num-fifos = <16>;
384 interrupt-parent = <&main_navss_intr>;
389 compatible = "ti,am654-navss-ringacc";
395 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
396 ti,num-rings = <1024>;
397 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
399 ti,sci-dev-id = <211>;
400 msi-parent = <&main_udmass_inta>;
403 main_udmap: dma-controller@31150000 {
404 compatible = "ti,j721e-navss-main-udmap";
411 reg-names = "gcfg", "rchanrt", "tchanrt",
413 msi-parent = <&main_udmass_inta>;
414 #dma-cells = <1>;
417 ti,sci-dev-id = <212>;
420 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
423 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
426 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
430 compatible = "ti,j721e-cpts";
432 reg-names = "cpts";
434 clock-names = "cpts";
435 interrupts-extended = <&main_navss_intr 391>;
436 interrupt-names = "cpts";
437 ti,cpts-periodic-outputs = <6>;
438 ti,cpts-ext-ts-inputs = <8>;
443 compatible = "ti,j721e-cpswxg-nuss";
444 #address-cells = <2>;
445 #size-cells = <2>;
447 reg-names = "cpsw_nuss";
450 clock-names = "fck";
451 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
462 dma-names = "tx0", "tx1", "tx2", "tx3",
468 ethernet-ports {
469 #address-cells = <1>;
470 #size-cells = <0>;
473 ti,mac-only;
480 ti,mac-only;
487 ti,mac-only;
494 ti,mac-only;
501 ti,mac-only;
508 ti,mac-only;
515 ti,mac-only;
522 ti,mac-only;
529 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
531 #address-cells = <1>;
532 #size-cells = <0>;
534 clock-names = "fck";
540 compatible = "ti,j721e-cpts";
543 clock-names = "cpts";
544 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
545 interrupt-names = "cpts";
546 ti,cpts-ext-ts-inputs = <4>;
547 ti,cpts-periodic-outputs = <2>;
552 compatible = "ti,j721e-sa2ul";
554 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
555 #address-cells = <2>;
556 #size-cells = <2>;
561 dma-names = "tx", "rx1", "rx2";
564 compatible = "inside-secure,safexcel-eip76";
571 compatible = "pinctrl-single";
574 #pinctrl-cells = <1>;
575 pinctrl-single,register-width = <32>;
576 pinctrl-single,function-mask = <0xffffffff>;
581 compatible = "pinctrl-single";
583 #pinctrl-cells = <1>;
584 pinctrl-single,register-width = <32>;
585 pinctrl-single,function-mask = <0x00000007>;
590 compatible = "pinctrl-single";
592 #pinctrl-cells = <1>;
593 pinctrl-single,register-width = <32>;
594 pinctrl-single,function-mask = <0x0000001f>;
598 compatible = "ti,j721e-csi2rx-shim";
601 #address-cells = <2>;
602 #size-cells = <2>;
604 dma-names = "rx0";
605 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
608 cdns_csi2rx0: csi-bridge@4504000 {
609 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
613 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
616 phy-names = "dphy";
619 #address-cells = <1>;
620 #size-cells = <0>;
651 compatible = "ti,j721e-csi2rx-shim";
654 #address-cells = <2>;
655 #size-cells = <2>;
657 dma-names = "rx0";
658 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
661 cdns_csi2rx1: csi-bridge@4514000 {
662 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
666 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
669 phy-names = "dphy";
672 #address-cells = <1>;
673 #size-cells = <0>;
704 compatible = "cdns,dphy-rx";
706 #phy-cells = <0>;
707 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
712 compatible = "cdns,dphy-rx";
714 #phy-cells = <0>;
715 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
720 compatible = "ti,j721e-wiz-16g";
721 #address-cells = <1>;
722 #size-cells = <1>;
723 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
725 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
726 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
727 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
728 num-lanes = <2>;
729 #reset-cells = <1>;
732 wiz0_pll0_refclk: pll0-refclk {
734 #clock-cells = <0>;
735 assigned-clocks = <&wiz0_pll0_refclk>;
736 assigned-clock-parents = <&k3_clks 292 11>;
739 wiz0_pll1_refclk: pll1-refclk {
741 #clock-cells = <0>;
742 assigned-clocks = <&wiz0_pll1_refclk>;
743 assigned-clock-parents = <&k3_clks 292 0>;
746 wiz0_refclk_dig: refclk-dig {
748 #clock-cells = <0>;
749 assigned-clocks = <&wiz0_refclk_dig>;
750 assigned-clock-parents = <&k3_clks 292 11>;
753 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
755 #clock-cells = <0>;
758 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
760 #clock-cells = <0>;
764 compatible = "ti,sierra-phy-t0";
765 reg-names = "serdes";
767 #address-cells = <1>;
768 #size-cells = <0>;
769 #clock-cells = <1>;
771 reset-names = "sierra_reset";
774 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
780 compatible = "ti,j721e-wiz-16g";
781 #address-cells = <1>;
782 #size-cells = <1>;
783 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
785 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
786 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
787 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
788 num-lanes = <2>;
789 #reset-cells = <1>;
792 wiz1_pll0_refclk: pll0-refclk {
794 #clock-cells = <0>;
795 assigned-clocks = <&wiz1_pll0_refclk>;
796 assigned-clock-parents = <&k3_clks 293 13>;
799 wiz1_pll1_refclk: pll1-refclk {
801 #clock-cells = <0>;
802 assigned-clocks = <&wiz1_pll1_refclk>;
803 assigned-clock-parents = <&k3_clks 293 0>;
806 wiz1_refclk_dig: refclk-dig {
808 #clock-cells = <0>;
809 assigned-clocks = <&wiz1_refclk_dig>;
810 assigned-clock-parents = <&k3_clks 293 13>;
813 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
815 #clock-cells = <0>;
818 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
820 #clock-cells = <0>;
824 compatible = "ti,sierra-phy-t0";
825 reg-names = "serdes";
827 #address-cells = <1>;
828 #size-cells = <0>;
829 #clock-cells = <1>;
831 reset-names = "sierra_reset";
834 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
840 compatible = "ti,j721e-wiz-16g";
841 #address-cells = <1>;
842 #size-cells = <1>;
843 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
845 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
846 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
847 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
848 num-lanes = <2>;
849 #reset-cells = <1>;
852 wiz2_pll0_refclk: pll0-refclk {
854 #clock-cells = <0>;
855 assigned-clocks = <&wiz2_pll0_refclk>;
856 assigned-clock-parents = <&k3_clks 294 11>;
859 wiz2_pll1_refclk: pll1-refclk {
861 #clock-cells = <0>;
862 assigned-clocks = <&wiz2_pll1_refclk>;
863 assigned-clock-parents = <&k3_clks 294 0>;
866 wiz2_refclk_dig: refclk-dig {
868 #clock-cells = <0>;
869 assigned-clocks = <&wiz2_refclk_dig>;
870 assigned-clock-parents = <&k3_clks 294 11>;
873 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
875 #clock-cells = <0>;
878 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
880 #clock-cells = <0>;
884 compatible = "ti,sierra-phy-t0";
885 reg-names = "serdes";
887 #address-cells = <1>;
888 #size-cells = <0>;
889 #clock-cells = <1>;
891 reset-names = "sierra_reset";
894 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
900 compatible = "ti,j721e-wiz-16g";
901 #address-cells = <1>;
902 #size-cells = <1>;
903 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
905 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
906 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
907 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
908 num-lanes = <2>;
909 #reset-cells = <1>;
912 wiz3_pll0_refclk: pll0-refclk {
914 #clock-cells = <0>;
915 assigned-clocks = <&wiz3_pll0_refclk>;
916 assigned-clock-parents = <&k3_clks 295 9>;
919 wiz3_pll1_refclk: pll1-refclk {
921 #clock-cells = <0>;
922 assigned-clocks = <&wiz3_pll1_refclk>;
923 assigned-clock-parents = <&k3_clks 295 0>;
926 wiz3_refclk_dig: refclk-dig {
928 #clock-cells = <0>;
929 assigned-clocks = <&wiz3_refclk_dig>;
930 assigned-clock-parents = <&k3_clks 295 9>;
933 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
935 #clock-cells = <0>;
938 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
940 #clock-cells = <0>;
944 compatible = "ti,sierra-phy-t0";
945 reg-names = "serdes";
947 #address-cells = <1>;
948 #size-cells = <0>;
949 #clock-cells = <1>;
951 reset-names = "sierra_reset";
954 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
960 compatible = "ti,j721e-pcie-host";
965 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
966 interrupt-names = "link_state";
969 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
970 max-link-speed = <3>;
971 num-lanes = <2>;
972 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
974 clock-names = "fck";
975 #address-cells = <3>;
976 #size-cells = <2>;
977 bus-range = <0x0 0xff>;
978 vendor-id = <0x104c>;
979 device-id = <0xb00d>;
980 msi-map = <0x0 &gic_its 0x0 0x10000>;
981 dma-coherent;
983 … 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4…
984 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
989 compatible = "ti,j721e-pcie-host";
994 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
995 interrupt-names = "link_state";
998 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
999 max-link-speed = <3>;
1000 num-lanes = <2>;
1001 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
1003 clock-names = "fck";
1004 #address-cells = <3>;
1005 #size-cells = <2>;
1006 bus-range = <0x0 0xff>;
1007 vendor-id = <0x104c>;
1008 device-id = <0xb00d>;
1009 msi-map = <0x0 &gic_its 0x10000 0x10000>;
1010 dma-coherent;
1012 … 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4…
1013 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1018 compatible = "ti,j721e-pcie-host";
1023 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1024 interrupt-names = "link_state";
1027 ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
1028 max-link-speed = <3>;
1029 num-lanes = <2>;
1030 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
1032 clock-names = "fck";
1033 #address-cells = <3>;
1034 #size-cells = <2>;
1035 bus-range = <0x0 0xff>;
1036 vendor-id = <0x104c>;
1037 device-id = <0xb00d>;
1038 msi-map = <0x0 &gic_its 0x20000 0x10000>;
1039 dma-coherent;
1042 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1047 compatible = "ti,j721e-pcie-host";
1052 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1053 interrupt-names = "link_state";
1056 ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
1057 max-link-speed = <3>;
1058 num-lanes = <2>;
1059 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
1061 clock-names = "fck";
1062 #address-cells = <3>;
1063 #size-cells = <2>;
1064 bus-range = <0x0 0xff>;
1065 vendor-id = <0x104c>;
1066 device-id = <0xb00d>;
1067 msi-map = <0x0 &gic_its 0x30000 0x10000>;
1068 dma-coherent;
1071 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1076 compatible = "ti,am64-wiz-10g";
1077 #address-cells = <1>;
1078 #size-cells = <1>;
1079 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
1081 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1082 assigned-clocks = <&k3_clks 297 9>;
1083 assigned-clock-parents = <&k3_clks 297 10>;
1084 assigned-clock-rates = <19200000>;
1085 num-lanes = <4>;
1086 #reset-cells = <1>;
1087 #clock-cells = <1>;
1096 compatible = "ti,j721e-serdes-10g";
1099 reg-names = "torrent_phy", "dptx_phy";
1102 reset-names = "torrent_reset";
1104 clock-names = "refclk";
1105 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
1108 assigned-clock-parents = <&k3_clks 297 9>,
1111 #address-cells = <1>;
1112 #size-cells = <0>;
1117 compatible = "ti,am654-timer";
1121 clock-names = "fck";
1122 assigned-clocks = <&k3_clks 49 1>;
1123 assigned-clock-parents = <&k3_clks 49 2>;
1124 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1125 ti,timer-pwm;
1129 compatible = "ti,am654-timer";
1133 clock-names = "fck";
1134 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
1135 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
1136 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1137 ti,timer-pwm;
1141 compatible = "ti,am654-timer";
1145 clock-names = "fck";
1146 assigned-clocks = <&k3_clks 51 1>;
1147 assigned-clock-parents = <&k3_clks 51 2>;
1148 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
1149 ti,timer-pwm;
1153 compatible = "ti,am654-timer";
1157 clock-names = "fck";
1158 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
1159 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
1160 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1161 ti,timer-pwm;
1165 compatible = "ti,am654-timer";
1169 clock-names = "fck";
1170 assigned-clocks = <&k3_clks 53 1>;
1171 assigned-clock-parents = <&k3_clks 53 2>;
1172 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1173 ti,timer-pwm;
1177 compatible = "ti,am654-timer";
1181 clock-names = "fck";
1182 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
1183 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
1184 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1185 ti,timer-pwm;
1189 compatible = "ti,am654-timer";
1193 clock-names = "fck";
1194 assigned-clocks = <&k3_clks 55 1>;
1195 assigned-clock-parents = <&k3_clks 55 2>;
1196 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1197 ti,timer-pwm;
1201 compatible = "ti,am654-timer";
1205 clock-names = "fck";
1206 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
1207 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
1208 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1209 ti,timer-pwm;
1213 compatible = "ti,am654-timer";
1217 clock-names = "fck";
1218 assigned-clocks = <&k3_clks 58 1>;
1219 assigned-clock-parents = <&k3_clks 58 2>;
1220 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1221 ti,timer-pwm;
1225 compatible = "ti,am654-timer";
1229 clock-names = "fck";
1230 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
1231 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
1232 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1233 ti,timer-pwm;
1237 compatible = "ti,am654-timer";
1241 clock-names = "fck";
1242 assigned-clocks = <&k3_clks 60 1>;
1243 assigned-clock-parents = <&k3_clks 60 2>;
1244 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1245 ti,timer-pwm;
1249 compatible = "ti,am654-timer";
1253 clock-names = "fck";
1254 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
1255 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
1256 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1257 ti,timer-pwm;
1261 compatible = "ti,am654-timer";
1265 clock-names = "fck";
1266 assigned-clocks = <&k3_clks 63 1>;
1267 assigned-clock-parents = <&k3_clks 63 2>;
1268 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1269 ti,timer-pwm;
1273 compatible = "ti,am654-timer";
1277 clock-names = "fck";
1278 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
1279 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
1280 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1281 ti,timer-pwm;
1285 compatible = "ti,am654-timer";
1289 clock-names = "fck";
1290 assigned-clocks = <&k3_clks 65 1>;
1291 assigned-clock-parents = <&k3_clks 65 2>;
1292 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1293 ti,timer-pwm;
1297 compatible = "ti,am654-timer";
1301 clock-names = "fck";
1302 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
1303 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
1304 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1305 ti,timer-pwm;
1309 compatible = "ti,am654-timer";
1313 clock-names = "fck";
1314 assigned-clocks = <&k3_clks 67 1>;
1315 assigned-clock-parents = <&k3_clks 67 2>;
1316 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1317 ti,timer-pwm;
1321 compatible = "ti,am654-timer";
1325 clock-names = "fck";
1326 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
1327 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
1328 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1329 ti,timer-pwm;
1333 compatible = "ti,am654-timer";
1337 clock-names = "fck";
1338 assigned-clocks = <&k3_clks 69 1>;
1339 assigned-clock-parents = <&k3_clks 69 2>;
1340 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1341 ti,timer-pwm;
1345 compatible = "ti,am654-timer";
1349 clock-names = "fck";
1350 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
1351 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
1352 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1353 ti,timer-pwm;
1357 compatible = "ti,j721e-uart", "ti,am654-uart";
1360 clock-frequency = <48000000>;
1361 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
1363 clock-names = "fclk";
1368 compatible = "ti,j721e-uart", "ti,am654-uart";
1371 clock-frequency = <48000000>;
1372 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1374 clock-names = "fclk";
1379 compatible = "ti,j721e-uart", "ti,am654-uart";
1382 clock-frequency = <48000000>;
1383 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
1385 clock-names = "fclk";
1390 compatible = "ti,j721e-uart", "ti,am654-uart";
1393 clock-frequency = <48000000>;
1394 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
1396 clock-names = "fclk";
1401 compatible = "ti,j721e-uart", "ti,am654-uart";
1404 clock-frequency = <48000000>;
1405 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
1407 clock-names = "fclk";
1412 compatible = "ti,j721e-uart", "ti,am654-uart";
1415 clock-frequency = <48000000>;
1416 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
1418 clock-names = "fclk";
1423 compatible = "ti,j721e-uart", "ti,am654-uart";
1426 clock-frequency = <48000000>;
1427 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
1429 clock-names = "fclk";
1434 compatible = "ti,j721e-uart", "ti,am654-uart";
1437 clock-frequency = <48000000>;
1438 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
1440 clock-names = "fclk";
1445 compatible = "ti,j721e-uart", "ti,am654-uart";
1448 clock-frequency = <48000000>;
1449 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
1451 clock-names = "fclk";
1456 compatible = "ti,j721e-uart", "ti,am654-uart";
1459 clock-frequency = <48000000>;
1460 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1462 clock-names = "fclk";
1466 main_gpio0: gpio@600000 {
1467 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1469 gpio-controller;
1470 #gpio-cells = <2>;
1471 interrupt-parent = <&main_gpio_intr>;
1474 interrupt-controller;
1475 #interrupt-cells = <2>;
1477 ti,davinci-gpio-unbanked = <0>;
1478 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
1480 clock-names = "gpio";
1484 main_gpio1: gpio@601000 {
1485 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1487 gpio-controller;
1488 #gpio-cells = <2>;
1489 interrupt-parent = <&main_gpio_intr>;
1491 interrupt-controller;
1492 #interrupt-cells = <2>;
1494 ti,davinci-gpio-unbanked = <0>;
1495 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
1497 clock-names = "gpio";
1501 main_gpio2: gpio@610000 {
1502 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1504 gpio-controller;
1505 #gpio-cells = <2>;
1506 interrupt-parent = <&main_gpio_intr>;
1509 interrupt-controller;
1510 #interrupt-cells = <2>;
1512 ti,davinci-gpio-unbanked = <0>;
1513 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
1515 clock-names = "gpio";
1519 main_gpio3: gpio@611000 {
1520 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1522 gpio-controller;
1523 #gpio-cells = <2>;
1524 interrupt-parent = <&main_gpio_intr>;
1526 interrupt-controller;
1527 #interrupt-cells = <2>;
1529 ti,davinci-gpio-unbanked = <0>;
1530 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1532 clock-names = "gpio";
1536 main_gpio4: gpio@620000 {
1537 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1539 gpio-controller;
1540 #gpio-cells = <2>;
1541 interrupt-parent = <&main_gpio_intr>;
1544 interrupt-controller;
1545 #interrupt-cells = <2>;
1547 ti,davinci-gpio-unbanked = <0>;
1548 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1550 clock-names = "gpio";
1554 main_gpio5: gpio@621000 {
1555 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1557 gpio-controller;
1558 #gpio-cells = <2>;
1559 interrupt-parent = <&main_gpio_intr>;
1561 interrupt-controller;
1562 #interrupt-cells = <2>;
1564 ti,davinci-gpio-unbanked = <0>;
1565 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1567 clock-names = "gpio";
1571 main_gpio6: gpio@630000 {
1572 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1574 gpio-controller;
1575 #gpio-cells = <2>;
1576 interrupt-parent = <&main_gpio_intr>;
1579 interrupt-controller;
1580 #interrupt-cells = <2>;
1582 ti,davinci-gpio-unbanked = <0>;
1583 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1585 clock-names = "gpio";
1589 main_gpio7: gpio@631000 {
1590 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1592 gpio-controller;
1593 #gpio-cells = <2>;
1594 interrupt-parent = <&main_gpio_intr>;
1596 interrupt-controller;
1597 #interrupt-cells = <2>;
1599 ti,davinci-gpio-unbanked = <0>;
1600 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1602 clock-names = "gpio";
1607 compatible = "ti,j721e-sdhci-8bit";
1610 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1611 clock-names = "clk_ahb", "clk_xin";
1613 assigned-clocks = <&k3_clks 91 1>;
1614 assigned-clock-parents = <&k3_clks 91 2>;
1615 bus-width = <8>;
1616 mmc-hs200-1_8v;
1617 mmc-ddr-1_8v;
1618 ti,otap-del-sel-legacy = <0x0>;
1619 ti,otap-del-sel-mmc-hs = <0x0>;
1620 ti,otap-del-sel-ddr52 = <0x5>;
1621 ti,otap-del-sel-hs200 = <0x6>;
1622 ti,otap-del-sel-hs400 = <0x0>;
1623 ti,itap-del-sel-legacy = <0x10>;
1624 ti,itap-del-sel-mmc-hs = <0xa>;
1625 ti,itap-del-sel-ddr52 = <0x3>;
1626 ti,trm-icp = <0x8>;
1627 dma-coherent;
1632 compatible = "ti,j721e-sdhci-4bit";
1635 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1636 clock-names = "clk_ahb", "clk_xin";
1638 assigned-clocks = <&k3_clks 92 0>;
1639 assigned-clock-parents = <&k3_clks 92 1>;
1640 ti,otap-del-sel-legacy = <0x0>;
1641 ti,otap-del-sel-sd-hs = <0x0>;
1642 ti,otap-del-sel-sdr12 = <0xf>;
1643 ti,otap-del-sel-sdr25 = <0xf>;
1644 ti,otap-del-sel-sdr50 = <0xc>;
1645 ti,otap-del-sel-ddr50 = <0xc>;
1646 ti,otap-del-sel-sdr104 = <0x5>;
1647 ti,itap-del-sel-legacy = <0x0>;
1648 ti,itap-del-sel-sd-hs = <0x0>;
1649 ti,itap-del-sel-sdr12 = <0x0>;
1650 ti,itap-del-sel-sdr25 = <0x0>;
1651 ti,itap-del-sel-ddr50 = <0x2>;
1652 ti,trm-icp = <0x8>;
1653 ti,clkbuf-sel = <0x7>;
1654 dma-coherent;
1655 sdhci-caps-mask = <0x2 0x0>;
1660 compatible = "ti,j721e-sdhci-4bit";
1663 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1664 clock-names = "clk_ahb", "clk_xin";
1666 assigned-clocks = <&k3_clks 93 0>;
1667 assigned-clock-parents = <&k3_clks 93 1>;
1668 ti,otap-del-sel-legacy = <0x0>;
1669 ti,otap-del-sel-sd-hs = <0x0>;
1670 ti,otap-del-sel-sdr12 = <0xf>;
1671 ti,otap-del-sel-sdr25 = <0xf>;
1672 ti,otap-del-sel-sdr50 = <0xc>;
1673 ti,otap-del-sel-ddr50 = <0xc>;
1674 ti,otap-del-sel-sdr104 = <0x5>;
1675 ti,itap-del-sel-legacy = <0x0>;
1676 ti,itap-del-sel-sd-hs = <0x0>;
1677 ti,itap-del-sel-sdr12 = <0x0>;
1678 ti,itap-del-sel-sdr25 = <0x0>;
1679 ti,itap-del-sel-ddr50 = <0x2>;
1680 ti,trm-icp = <0x8>;
1681 ti,clkbuf-sel = <0x7>;
1682 dma-coherent;
1683 sdhci-caps-mask = <0x2 0x0>;
1687 usbss0: cdns-usb@4104000 {
1688 compatible = "ti,j721e-usb";
1690 dma-coherent;
1691 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1693 clock-names = "ref", "lpm";
1694 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
1695 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1696 #address-cells = <2>;
1697 #size-cells = <2>;
1705 reg-names = "otg", "xhci", "dev";
1709 interrupt-names = "host",
1712 maximum-speed = "super-speed";
1717 usbss1: cdns-usb@4114000 {
1718 compatible = "ti,j721e-usb";
1720 dma-coherent;
1721 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1723 clock-names = "ref", "lpm";
1724 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
1725 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1726 #address-cells = <2>;
1727 #size-cells = <2>;
1735 reg-names = "otg", "xhci", "dev";
1739 interrupt-names = "host",
1742 maximum-speed = "super-speed";
1748 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1751 #address-cells = <1>;
1752 #size-cells = <0>;
1753 clock-names = "fck";
1755 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1760 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1765 clock-names = "fck";
1767 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1772 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1775 #address-cells = <1>;
1776 #size-cells = <0>;
1777 clock-names = "fck";
1779 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1784 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1787 #address-cells = <1>;
1788 #size-cells = <0>;
1789 clock-names = "fck";
1791 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1796 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1799 #address-cells = <1>;
1800 #size-cells = <0>;
1801 clock-names = "fck";
1803 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1808 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1811 #address-cells = <1>;
1812 #size-cells = <0>;
1813 clock-names = "fck";
1815 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1820 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1823 #address-cells = <1>;
1824 #size-cells = <0>;
1825 clock-names = "fck";
1827 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1831 ufs_wrapper: ufs-wrapper@4e80000 {
1832 compatible = "ti,j721e-ufs";
1834 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1836 assigned-clocks = <&k3_clks 277 1>;
1837 assigned-clock-parents = <&k3_clks 277 4>;
1839 #address-cells = <2>;
1840 #size-cells = <2>;
1843 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1846 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1848 clock-names = "core_clk", "phy_clk", "ref_clk";
1849 dma-coherent;
1853 mhdp: dp-bridge@a000000 {
1854 compatible = "ti,j721e-mhdp8546";
1861 reg-names = "mhdptx", "j721e-intg";
1865 interrupt-parent = <&gic500>;
1868 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1871 #address-cells = <1>;
1872 #size-cells = <0>;
1885 compatible = "ti,j721e-dss";
1908 reg-names = "common_m", "common_s0",
1920 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1922 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1928 interrupt-names = "common_m",
1938 compatible = "ti,am33xx-mcasp-audio";
1941 reg-names = "mpu","dat";
1944 interrupt-names = "tx", "rx";
1947 dma-names = "tx", "rx";
1950 clock-names = "fck";
1951 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1956 compatible = "ti,am33xx-mcasp-audio";
1959 reg-names = "mpu","dat";
1962 interrupt-names = "tx", "rx";
1965 dma-names = "tx", "rx";
1968 clock-names = "fck";
1969 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1974 compatible = "ti,am33xx-mcasp-audio";
1977 reg-names = "mpu","dat";
1980 interrupt-names = "tx", "rx";
1983 dma-names = "tx", "rx";
1986 clock-names = "fck";
1987 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1992 compatible = "ti,am33xx-mcasp-audio";
1995 reg-names = "mpu","dat";
1998 interrupt-names = "tx", "rx";
2001 dma-names = "tx", "rx";
2004 clock-names = "fck";
2005 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
2010 compatible = "ti,am33xx-mcasp-audio";
2013 reg-names = "mpu","dat";
2016 interrupt-names = "tx", "rx";
2019 dma-names = "tx", "rx";
2022 clock-names = "fck";
2023 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
2028 compatible = "ti,am33xx-mcasp-audio";
2031 reg-names = "mpu","dat";
2034 interrupt-names = "tx", "rx";
2037 dma-names = "tx", "rx";
2040 clock-names = "fck";
2041 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
2046 compatible = "ti,am33xx-mcasp-audio";
2049 reg-names = "mpu","dat";
2052 interrupt-names = "tx", "rx";
2055 dma-names = "tx", "rx";
2058 clock-names = "fck";
2059 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
2064 compatible = "ti,am33xx-mcasp-audio";
2067 reg-names = "mpu","dat";
2070 interrupt-names = "tx", "rx";
2073 dma-names = "tx", "rx";
2076 clock-names = "fck";
2077 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
2082 compatible = "ti,am33xx-mcasp-audio";
2085 reg-names = "mpu","dat";
2088 interrupt-names = "tx", "rx";
2091 dma-names = "tx", "rx";
2094 clock-names = "fck";
2095 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
2100 compatible = "ti,am33xx-mcasp-audio";
2103 reg-names = "mpu","dat";
2106 interrupt-names = "tx", "rx";
2109 dma-names = "tx", "rx";
2112 clock-names = "fck";
2113 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
2118 compatible = "ti,am33xx-mcasp-audio";
2121 reg-names = "mpu","dat";
2124 interrupt-names = "tx", "rx";
2127 dma-names = "tx", "rx";
2130 clock-names = "fck";
2131 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
2136 compatible = "ti,am33xx-mcasp-audio";
2139 reg-names = "mpu","dat";
2142 interrupt-names = "tx", "rx";
2145 dma-names = "tx", "rx";
2148 clock-names = "fck";
2149 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
2154 compatible = "ti,j7-rti-wdt";
2157 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
2158 assigned-clocks = <&k3_clks 252 1>;
2159 assigned-clock-parents = <&k3_clks 252 5>;
2163 compatible = "ti,j7-rti-wdt";
2166 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
2167 assigned-clocks = <&k3_clks 253 1>;
2168 assigned-clock-parents = <&k3_clks 253 5>;
2172 compatible = "ti,j721e-r5fss";
2173 ti,cluster-mode = <1>;
2174 #address-cells = <1>;
2175 #size-cells = <1>;
2178 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
2181 compatible = "ti,j721e-r5f";
2184 reg-names = "atcm", "btcm";
2186 ti,sci-dev-id = <245>;
2187 ti,sci-proc-ids = <0x06 0xff>;
2189 firmware-name = "j7-main-r5f0_0-fw";
2190 ti,atcm-enable = <1>;
2191 ti,btcm-enable = <1>;
2196 compatible = "ti,j721e-r5f";
2199 reg-names = "atcm", "btcm";
2201 ti,sci-dev-id = <246>;
2202 ti,sci-proc-ids = <0x07 0xff>;
2204 firmware-name = "j7-main-r5f0_1-fw";
2205 ti,atcm-enable = <1>;
2206 ti,btcm-enable = <1>;
2212 compatible = "ti,j721e-r5fss";
2213 ti,cluster-mode = <1>;
2214 #address-cells = <1>;
2215 #size-cells = <1>;
2218 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
2221 compatible = "ti,j721e-r5f";
2224 reg-names = "atcm", "btcm";
2226 ti,sci-dev-id = <247>;
2227 ti,sci-proc-ids = <0x08 0xff>;
2229 firmware-name = "j7-main-r5f1_0-fw";
2230 ti,atcm-enable = <1>;
2231 ti,btcm-enable = <1>;
2236 compatible = "ti,j721e-r5f";
2239 reg-names = "atcm", "btcm";
2241 ti,sci-dev-id = <248>;
2242 ti,sci-proc-ids = <0x09 0xff>;
2244 firmware-name = "j7-main-r5f1_1-fw";
2245 ti,atcm-enable = <1>;
2246 ti,btcm-enable = <1>;
2251 c66_0: dsp@4d80800000 {
2252 compatible = "ti,j721e-c66-dsp";
2256 reg-names = "l2sram", "l1pram", "l1dram";
2258 ti,sci-dev-id = <142>;
2259 ti,sci-proc-ids = <0x03 0xff>;
2261 firmware-name = "j7-c66_0-fw";
2265 c66_1: dsp@4d81800000 {
2266 compatible = "ti,j721e-c66-dsp";
2270 reg-names = "l2sram", "l1pram", "l1dram";
2272 ti,sci-dev-id = <143>;
2273 ti,sci-proc-ids = <0x04 0xff>;
2275 firmware-name = "j7-c66_1-fw";
2279 c71_0: dsp@64800000 {
2280 compatible = "ti,j721e-c71-dsp";
2283 reg-names = "l2sram", "l1dram";
2285 ti,sci-dev-id = <15>;
2286 ti,sci-proc-ids = <0x30 0xff>;
2288 firmware-name = "j7-c71_0-fw";
2293 compatible = "ti,j721e-icssg";
2295 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
2296 #address-cells = <1>;
2297 #size-cells = <1>;
2304 reg-names = "dram0", "dram1",
2309 compatible = "ti,pruss-cfg", "syscon";
2311 #address-cells = <1>;
2312 #size-cells = <1>;
2316 #address-cells = <1>;
2317 #size-cells = <0>;
2319 icssg0_coreclk_mux: coreclk-mux@3c {
2321 #clock-cells = <0>;
2324 assigned-clocks = <&icssg0_coreclk_mux>;
2325 assigned-clock-parents = <&k3_clks 119 1>;
2328 icssg0_iepclk_mux: iepclk-mux@30 {
2330 #clock-cells = <0>;
2333 assigned-clocks = <&icssg0_iepclk_mux>;
2334 assigned-clock-parents = <&icssg0_coreclk_mux>;
2339 icssg0_mii_rt: mii-rt@32000 {
2340 compatible = "ti,pruss-mii", "syscon";
2344 icssg0_mii_g_rt: mii-g-rt@33000 {
2345 compatible = "ti,pruss-mii-g", "syscon";
2349 icssg0_intc: interrupt-controller@20000 {
2350 compatible = "ti,icssg-intc";
2352 interrupt-controller;
2353 #interrupt-cells = <3>;
2362 interrupt-names = "host_intr0", "host_intr1",
2369 compatible = "ti,j721e-pru";
2373 reg-names = "iram", "control", "debug";
2374 firmware-name = "j7-pru0_0-fw";
2378 compatible = "ti,j721e-rtu";
2382 reg-names = "iram", "control", "debug";
2383 firmware-name = "j7-rtu0_0-fw";
2387 compatible = "ti,j721e-tx-pru";
2391 reg-names = "iram", "control", "debug";
2392 firmware-name = "j7-txpru0_0-fw";
2396 compatible = "ti,j721e-pru";
2400 reg-names = "iram", "control", "debug";
2401 firmware-name = "j7-pru0_1-fw";
2405 compatible = "ti,j721e-rtu";
2409 reg-names = "iram", "control", "debug";
2410 firmware-name = "j7-rtu0_1-fw";
2414 compatible = "ti,j721e-tx-pru";
2418 reg-names = "iram", "control", "debug";
2419 firmware-name = "j7-txpru0_1-fw";
2426 clock-names = "fck";
2427 #address-cells = <1>;
2428 #size-cells = <0>;
2435 compatible = "ti,j721e-icssg";
2437 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
2438 #address-cells = <1>;
2439 #size-cells = <1>;
2446 reg-names = "dram0", "dram1",
2451 compatible = "ti,pruss-cfg", "syscon";
2453 #address-cells = <1>;
2454 #size-cells = <1>;
2458 #address-cells = <1>;
2459 #size-cells = <0>;
2461 icssg1_coreclk_mux: coreclk-mux@3c {
2463 #clock-cells = <0>;
2466 assigned-clocks = <&icssg1_coreclk_mux>;
2467 assigned-clock-parents = <&k3_clks 120 4>;
2470 icssg1_iepclk_mux: iepclk-mux@30 {
2472 #clock-cells = <0>;
2475 assigned-clocks = <&icssg1_iepclk_mux>;
2476 assigned-clock-parents = <&icssg1_coreclk_mux>;
2481 icssg1_mii_rt: mii-rt@32000 {
2482 compatible = "ti,pruss-mii", "syscon";
2486 icssg1_mii_g_rt: mii-g-rt@33000 {
2487 compatible = "ti,pruss-mii-g", "syscon";
2491 icssg1_intc: interrupt-controller@20000 {
2492 compatible = "ti,icssg-intc";
2494 interrupt-controller;
2495 #interrupt-cells = <3>;
2504 interrupt-names = "host_intr0", "host_intr1",
2511 compatible = "ti,j721e-pru";
2515 reg-names = "iram", "control", "debug";
2516 firmware-name = "j7-pru1_0-fw";
2520 compatible = "ti,j721e-rtu";
2524 reg-names = "iram", "control", "debug";
2525 firmware-name = "j7-rtu1_0-fw";
2529 compatible = "ti,j721e-tx-pru";
2533 reg-names = "iram", "control", "debug";
2534 firmware-name = "j7-txpru1_0-fw";
2538 compatible = "ti,j721e-pru";
2542 reg-names = "iram", "control", "debug";
2543 firmware-name = "j7-pru1_1-fw";
2547 compatible = "ti,j721e-rtu";
2551 reg-names = "iram", "control", "debug";
2552 firmware-name = "j7-rtu1_1-fw";
2556 compatible = "ti,j721e-tx-pru";
2560 reg-names = "iram", "control", "debug";
2561 firmware-name = "j7-txpru1_1-fw";
2568 clock-names = "fck";
2569 #address-cells = <1>;
2570 #size-cells = <0>;
2580 reg-names = "m_can", "message_ram";
2581 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
2583 clock-names = "hclk", "cclk";
2586 interrupt-names = "int0", "int1";
2587 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2595 reg-names = "m_can", "message_ram";
2596 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
2598 clock-names = "hclk", "cclk";
2601 interrupt-names = "int0", "int1";
2602 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2610 reg-names = "m_can", "message_ram";
2611 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
2613 clock-names = "hclk", "cclk";
2616 interrupt-names = "int0", "int1";
2617 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2625 reg-names = "m_can", "message_ram";
2626 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
2628 clock-names = "hclk", "cclk";
2631 interrupt-names = "int0", "int1";
2632 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2640 reg-names = "m_can", "message_ram";
2641 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
2643 clock-names = "hclk", "cclk";
2646 interrupt-names = "int0", "int1";
2647 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2655 reg-names = "m_can", "message_ram";
2656 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
2658 clock-names = "hclk", "cclk";
2661 interrupt-names = "int0", "int1";
2662 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2670 reg-names = "m_can", "message_ram";
2671 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
2673 clock-names = "hclk", "cclk";
2676 interrupt-names = "int0", "int1";
2677 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2685 reg-names = "m_can", "message_ram";
2686 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
2688 clock-names = "hclk", "cclk";
2691 interrupt-names = "int0", "int1";
2692 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2700 reg-names = "m_can", "message_ram";
2701 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
2703 clock-names = "hclk", "cclk";
2706 interrupt-names = "int0", "int1";
2707 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2715 reg-names = "m_can", "message_ram";
2716 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
2718 clock-names = "hclk", "cclk";
2721 interrupt-names = "int0", "int1";
2722 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2730 reg-names = "m_can", "message_ram";
2731 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
2733 clock-names = "hclk", "cclk";
2736 interrupt-names = "int0", "int1";
2737 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2745 reg-names = "m_can", "message_ram";
2746 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
2748 clock-names = "hclk", "cclk";
2751 interrupt-names = "int0", "int1";
2752 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2760 reg-names = "m_can", "message_ram";
2761 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
2763 clock-names = "hclk", "cclk";
2766 interrupt-names = "int0", "int1";
2767 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2775 reg-names = "m_can", "message_ram";
2776 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
2778 clock-names = "hclk", "cclk";
2781 interrupt-names = "int0", "int1";
2782 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2787 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2790 #address-cells = <1>;
2791 #size-cells = <0>;
2792 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
2798 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2801 #address-cells = <1>;
2802 #size-cells = <0>;
2803 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
2809 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2812 #address-cells = <1>;
2813 #size-cells = <0>;
2814 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
2820 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2823 #address-cells = <1>;
2824 #size-cells = <0>;
2825 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
2831 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2834 #address-cells = <1>;
2835 #size-cells = <0>;
2836 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
2842 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2845 #address-cells = <1>;
2846 #size-cells = <0>;
2847 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
2853 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2856 #address-cells = <1>;
2857 #size-cells = <0>;
2858 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
2864 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2867 #address-cells = <1>;
2868 #size-cells = <0>;
2869 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
2875 compatible = "ti,j721e-esm";
2877 bootph-pre-ram;
2878 ti,esm-pins = <344>, <345>;