Lines Matching +full:0 +full:x33d00000
15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
49 reg = <0x4080 0x50>;
51 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
52 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
53 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
54 <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */
55 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
56 <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */
68 reg = <0x4044 0x20>;
74 reg = <0x4000 0x20>;
76 mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */
77 <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */
82 reg = <0x4140 0x18>;
90 reg = <0x00 0x3000000 0x00 0x100>;
92 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
100 reg = <0x00 0x3010000 0x00 0x100>;
102 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
110 reg = <0x00 0x3020000 0x00 0x100>;
112 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
120 reg = <0x00 0x3030000 0x00 0x100>;
122 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
130 reg = <0x00 0x3040000 0x00 0x100>;
132 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
140 reg = <0x00 0x3050000 0x00 0x100>;
142 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
154 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
155 <0x00 0x01900000 0x00 0x100000>, /* GICR */
156 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
157 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
158 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
165 reg = <0x00 0x01820000 0x00 0x10000>;
166 socionext,synquacer-pre-its = <0x1000000 0x400000>;
174 reg = <0x00 0x00a00000 0x00 0x800>;
188 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
196 reg = <0x0 0x310e0000 0x0 0x4000>;
203 ti,interrupt-ranges = <0 64 64>,
210 reg = <0x0 0x33d00000 0x0 0x100000>;
214 #interrupt-cells = <0>;
217 ti,interrupt-ranges = <0 0 256>;
224 reg = <0x00 0x32c00000 0x00 0x100000>,
225 <0x00 0x32400000 0x00 0x100000>,
226 <0x00 0x32800000 0x00 0x100000>;
233 reg = <0x0 0x36600000 0x0 0x100000>;
243 reg = <0x00 0x30e00000 0x00 0x1000>;
249 reg = <0x00 0x31f80000 0x00 0x200>;
259 reg = <0x00 0x31f81000 0x00 0x200>;
269 reg = <0x00 0x31f82000 0x00 0x200>;
279 reg = <0x00 0x31f83000 0x00 0x200>;
289 reg = <0x00 0x31f84000 0x00 0x200>;
299 reg = <0x00 0x31f85000 0x00 0x200>;
309 reg = <0x00 0x31f86000 0x00 0x200>;
319 reg = <0x00 0x31f87000 0x00 0x200>;
329 reg = <0x00 0x31f88000 0x00 0x200>;
339 reg = <0x00 0x31f89000 0x00 0x200>;
349 reg = <0x00 0x31f8a000 0x00 0x200>;
359 reg = <0x00 0x31f8b000 0x00 0x200>;
369 reg = <0x0 0x3c000000 0x0 0x400000>,
370 <0x0 0x38000000 0x0 0x400000>,
371 <0x0 0x31120000 0x0 0x100>,
372 <0x0 0x33000000 0x0 0x40000>,
373 <0x0 0x31080000 0x0 0x40000>;
376 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
384 reg = <0x0 0x31150000 0x0 0x100>,
385 <0x0 0x34000000 0x0 0x100000>,
386 <0x0 0x35000000 0x0 0x100000>,
387 <0x0 0x30b00000 0x0 0x20000>,
388 <0x0 0x30c00000 0x0 0x10000>,
389 <0x0 0x30d00000 0x0 0x8000>;
399 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
400 <0x0f>, /* TX_HCHAN */
401 <0x10>; /* TX_UHCHAN */
402 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
403 <0x0b>, /* RX_HCHAN */
404 <0x0c>; /* RX_UHCHAN */
405 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
410 reg = <0x0 0x310d0000 0x0 0x400>;
425 reg = <0x0 0xc000000 0x0 0x200000>;
427 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
432 dmas = <&main_udmap 0xca00>,
433 <&main_udmap 0xca01>,
434 <&main_udmap 0xca02>,
435 <&main_udmap 0xca03>,
436 <&main_udmap 0xca04>,
437 <&main_udmap 0xca05>,
438 <&main_udmap 0xca06>,
439 <&main_udmap 0xca07>,
440 <&main_udmap 0x4a00>;
449 #size-cells = <0>;
509 reg = <0x0 0xf00 0x0 0x100>;
511 #size-cells = <0>;
520 reg = <0x0 0x3d000 0x0 0x400>;
532 reg = <0x0 0x4e00000 0x0 0x1200>;
536 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
538 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
539 <&main_udmap 0x4001>;
544 reg = <0x0 0x4e10000 0x0 0x7d>;
551 /* Proxy 0 addressing */
552 reg = <0x0 0x11c000 0x0 0x2b4>;
555 pinctrl-single,function-mask = <0xffffffff>;
561 reg = <0x00 0x104200 0x00 0x50>;
564 pinctrl-single,function-mask = <0x00000007>;
570 reg = <0x00 0x104280 0x00 0x20>;
573 pinctrl-single,function-mask = <0x0000001f>;
578 reg = <0x0 0x4500000 0x0 0x1000>;
582 dmas = <&main_udmap 0x4940>;
589 reg = <0x0 0x4504000 0x0 0x1000>;
590 clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
599 #size-cells = <0>;
601 csi0_port0: port@0 {
602 reg = <0>;
631 reg = <0x0 0x4510000 0x0 0x1000>;
635 dmas = <&main_udmap 0x4960>;
642 reg = <0x0 0x4514000 0x0 0x1000>;
643 clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,
652 #size-cells = <0>;
654 csi1_port0: port@0 {
655 reg = <0>;
684 reg = <0x0 0x4580000 0x0 0x1100>;
685 #phy-cells = <0>;
692 reg = <0x0 0x4590000 0x0 0x1100>;
693 #phy-cells = <0>;
705 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
709 ranges = <0x5000000 0x0 0x5000000 0x10000>;
713 #clock-cells = <0>;
719 clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
720 #clock-cells = <0>;
722 assigned-clock-parents = <&k3_clks 292 0>;
726 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
727 #clock-cells = <0>;
734 #clock-cells = <0>;
739 #clock-cells = <0>;
745 reg = <0x5000000 0x10000>;
747 #size-cells = <0>;
749 resets = <&serdes_wiz0 0>;
765 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
769 ranges = <0x5010000 0x0 0x5010000 0x10000>;
773 #clock-cells = <0>;
779 clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
780 #clock-cells = <0>;
782 assigned-clock-parents = <&k3_clks 293 0>;
786 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
787 #clock-cells = <0>;
794 #clock-cells = <0>;
799 #clock-cells = <0>;
805 reg = <0x5010000 0x10000>;
807 #size-cells = <0>;
809 resets = <&serdes_wiz1 0>;
825 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
829 ranges = <0x5020000 0x0 0x5020000 0x10000>;
833 #clock-cells = <0>;
839 clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
840 #clock-cells = <0>;
842 assigned-clock-parents = <&k3_clks 294 0>;
846 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
847 #clock-cells = <0>;
854 #clock-cells = <0>;
859 #clock-cells = <0>;
865 reg = <0x5020000 0x10000>;
867 #size-cells = <0>;
869 resets = <&serdes_wiz2 0>;
885 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
889 ranges = <0x5030000 0x0 0x5030000 0x10000>;
893 #clock-cells = <0>;
899 clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
900 #clock-cells = <0>;
902 assigned-clock-parents = <&k3_clks 295 0>;
906 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
907 #clock-cells = <0>;
914 #clock-cells = <0>;
919 #clock-cells = <0>;
925 reg = <0x5030000 0x10000>;
927 #size-cells = <0>;
929 resets = <&serdes_wiz3 0>;
940 reg = <0x00 0x02900000 0x00 0x1000>,
941 <0x00 0x02907000 0x00 0x400>,
942 <0x00 0x0d000000 0x00 0x00800000>,
943 <0x00 0x10000000 0x00 0x00001000>;
948 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
956 bus-range = <0x0 0xff>;
957 vendor-id = <0x104c>;
958 device-id = <0xb00d>;
959 msi-map = <0x0 &gic_its 0x0 0x10000>;
961 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
962 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
963 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
969 reg = <0x00 0x02910000 0x00 0x1000>,
970 <0x00 0x02917000 0x00 0x400>,
971 <0x00 0x0d800000 0x00 0x00800000>,
972 <0x00 0x18000000 0x00 0x00001000>;
977 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
985 bus-range = <0x0 0xff>;
986 vendor-id = <0x104c>;
987 device-id = <0xb00d>;
988 msi-map = <0x0 &gic_its 0x10000 0x10000>;
990 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
991 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
992 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
998 reg = <0x00 0x02920000 0x00 0x1000>,
999 <0x00 0x02927000 0x00 0x400>,
1000 <0x00 0x0e000000 0x00 0x00800000>,
1001 <0x44 0x00000000 0x00 0x00001000>;
1006 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
1014 bus-range = <0x0 0xff>;
1015 vendor-id = <0x104c>;
1016 device-id = <0xb00d>;
1017 msi-map = <0x0 &gic_its 0x20000 0x10000>;
1019 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
1020 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
1021 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1027 reg = <0x00 0x02930000 0x00 0x1000>,
1028 <0x00 0x02937000 0x00 0x400>,
1029 <0x00 0x0e800000 0x00 0x00800000>,
1030 <0x44 0x10000000 0x00 0x00001000>;
1035 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
1043 bus-range = <0x0 0xff>;
1044 vendor-id = <0x104c>;
1045 device-id = <0xb00d>;
1046 msi-map = <0x0 &gic_its 0x30000 0x10000>;
1048 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
1049 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
1050 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1067 ranges = <0x05050000 0x00 0x05050000 0x010000>,
1068 <0x0a030a00 0x00 0x0a030a00 0x40>;
1076 reg = <0x05050000 0x010000>,
1077 <0x0a030a00 0x40>; /* DPTX PHY */
1080 resets = <&serdes_wiz4 0>;
1091 #size-cells = <0>;
1097 reg = <0x00 0x2400000 0x00 0x400>;
1109 reg = <0x00 0x2410000 0x00 0x400>;
1113 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
1121 reg = <0x00 0x2420000 0x00 0x400>;
1133 reg = <0x00 0x2430000 0x00 0x400>;
1137 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
1145 reg = <0x00 0x2440000 0x00 0x400>;
1157 reg = <0x00 0x2450000 0x00 0x400>;
1161 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
1169 reg = <0x00 0x2460000 0x00 0x400>;
1181 reg = <0x00 0x2470000 0x00 0x400>;
1185 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
1193 reg = <0x00 0x2480000 0x00 0x400>;
1205 reg = <0x00 0x2490000 0x00 0x400>;
1209 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
1217 reg = <0x00 0x24a0000 0x00 0x400>;
1229 reg = <0x00 0x24b0000 0x00 0x400>;
1233 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
1241 reg = <0x00 0x24c0000 0x00 0x400>;
1253 reg = <0x00 0x24d0000 0x00 0x400>;
1257 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
1265 reg = <0x00 0x24e0000 0x00 0x400>;
1277 reg = <0x00 0x24f0000 0x00 0x400>;
1281 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
1289 reg = <0x00 0x2500000 0x00 0x400>;
1301 reg = <0x00 0x2510000 0x00 0x400>;
1305 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
1313 reg = <0x00 0x2520000 0x00 0x400>;
1325 reg = <0x00 0x2530000 0x00 0x400>;
1329 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
1337 reg = <0x00 0x02800000 0x00 0x100>;
1341 clocks = <&k3_clks 146 0>;
1348 reg = <0x00 0x02810000 0x00 0x100>;
1352 clocks = <&k3_clks 278 0>;
1359 reg = <0x00 0x02820000 0x00 0x100>;
1363 clocks = <&k3_clks 279 0>;
1370 reg = <0x00 0x02830000 0x00 0x100>;
1374 clocks = <&k3_clks 280 0>;
1381 reg = <0x00 0x02840000 0x00 0x100>;
1385 clocks = <&k3_clks 281 0>;
1392 reg = <0x00 0x02850000 0x00 0x100>;
1396 clocks = <&k3_clks 282 0>;
1403 reg = <0x00 0x02860000 0x00 0x100>;
1407 clocks = <&k3_clks 283 0>;
1414 reg = <0x00 0x02870000 0x00 0x100>;
1418 clocks = <&k3_clks 284 0>;
1425 reg = <0x00 0x02880000 0x00 0x100>;
1429 clocks = <&k3_clks 285 0>;
1436 reg = <0x00 0x02890000 0x00 0x100>;
1440 clocks = <&k3_clks 286 0>;
1447 reg = <0x0 0x00600000 0x0 0x100>;
1456 ti,davinci-gpio-unbanked = <0>;
1458 clocks = <&k3_clks 105 0>;
1465 reg = <0x0 0x00601000 0x0 0x100>;
1473 ti,davinci-gpio-unbanked = <0>;
1475 clocks = <&k3_clks 106 0>;
1482 reg = <0x0 0x00610000 0x0 0x100>;
1491 ti,davinci-gpio-unbanked = <0>;
1493 clocks = <&k3_clks 107 0>;
1500 reg = <0x0 0x00611000 0x0 0x100>;
1508 ti,davinci-gpio-unbanked = <0>;
1510 clocks = <&k3_clks 108 0>;
1517 reg = <0x0 0x00620000 0x0 0x100>;
1526 ti,davinci-gpio-unbanked = <0>;
1528 clocks = <&k3_clks 109 0>;
1535 reg = <0x0 0x00621000 0x0 0x100>;
1543 ti,davinci-gpio-unbanked = <0>;
1545 clocks = <&k3_clks 110 0>;
1552 reg = <0x0 0x00630000 0x0 0x100>;
1561 ti,davinci-gpio-unbanked = <0>;
1563 clocks = <&k3_clks 111 0>;
1570 reg = <0x0 0x00631000 0x0 0x100>;
1578 ti,davinci-gpio-unbanked = <0>;
1580 clocks = <&k3_clks 112 0>;
1587 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1591 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
1597 ti,otap-del-sel-legacy = <0x0>;
1598 ti,otap-del-sel-mmc-hs = <0x0>;
1599 ti,otap-del-sel-ddr52 = <0x5>;
1600 ti,otap-del-sel-hs200 = <0x6>;
1601 ti,otap-del-sel-hs400 = <0x0>;
1602 ti,itap-del-sel-legacy = <0x10>;
1603 ti,itap-del-sel-mmc-hs = <0xa>;
1604 ti,itap-del-sel-ddr52 = <0x3>;
1605 ti,trm-icp = <0x8>;
1612 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1616 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
1617 assigned-clocks = <&k3_clks 92 0>;
1619 ti,otap-del-sel-legacy = <0x0>;
1620 ti,otap-del-sel-sd-hs = <0x0>;
1621 ti,otap-del-sel-sdr12 = <0xf>;
1622 ti,otap-del-sel-sdr25 = <0xf>;
1623 ti,otap-del-sel-sdr50 = <0xc>;
1624 ti,otap-del-sel-ddr50 = <0xc>;
1625 ti,otap-del-sel-sdr104 = <0x5>;
1626 ti,itap-del-sel-legacy = <0x0>;
1627 ti,itap-del-sel-sd-hs = <0x0>;
1628 ti,itap-del-sel-sdr12 = <0x0>;
1629 ti,itap-del-sel-sdr25 = <0x0>;
1630 ti,itap-del-sel-ddr50 = <0x2>;
1631 ti,trm-icp = <0x8>;
1632 ti,clkbuf-sel = <0x7>;
1634 sdhci-caps-mask = <0x2 0x0>;
1640 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1644 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
1645 assigned-clocks = <&k3_clks 93 0>;
1647 ti,otap-del-sel-legacy = <0x0>;
1648 ti,otap-del-sel-sd-hs = <0x0>;
1649 ti,otap-del-sel-sdr12 = <0xf>;
1650 ti,otap-del-sel-sdr25 = <0xf>;
1651 ti,otap-del-sel-sdr50 = <0xc>;
1652 ti,otap-del-sel-ddr50 = <0xc>;
1653 ti,otap-del-sel-sdr104 = <0x5>;
1654 ti,itap-del-sel-legacy = <0x0>;
1655 ti,itap-del-sel-sd-hs = <0x0>;
1656 ti,itap-del-sel-sdr12 = <0x0>;
1657 ti,itap-del-sel-sdr25 = <0x0>;
1658 ti,itap-del-sel-ddr50 = <0x2>;
1659 ti,trm-icp = <0x8>;
1660 ti,clkbuf-sel = <0x7>;
1662 sdhci-caps-mask = <0x2 0x0>;
1668 reg = <0x00 0x4104000 0x00 0x100>;
1681 reg = <0x00 0x6000000 0x00 0x10000>,
1682 <0x00 0x6010000 0x00 0x10000>,
1683 <0x00 0x6020000 0x00 0x10000>;
1685 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1687 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1698 reg = <0x00 0x4114000 0x00 0x100>;
1711 reg = <0x00 0x6400000 0x00 0x10000>,
1712 <0x00 0x6410000 0x00 0x10000>,
1713 <0x00 0x6420000 0x00 0x10000>;
1715 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1717 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1728 reg = <0x0 0x2000000 0x0 0x100>;
1731 #size-cells = <0>;
1733 clocks = <&k3_clks 187 0>;
1740 reg = <0x0 0x2010000 0x0 0x100>;
1743 #size-cells = <0>;
1745 clocks = <&k3_clks 188 0>;
1752 reg = <0x0 0x2020000 0x0 0x100>;
1755 #size-cells = <0>;
1757 clocks = <&k3_clks 189 0>;
1764 reg = <0x0 0x2030000 0x0 0x100>;
1767 #size-cells = <0>;
1769 clocks = <&k3_clks 190 0>;
1776 reg = <0x0 0x2040000 0x0 0x100>;
1779 #size-cells = <0>;
1781 clocks = <&k3_clks 191 0>;
1788 reg = <0x0 0x2050000 0x0 0x100>;
1791 #size-cells = <0>;
1793 clocks = <&k3_clks 192 0>;
1800 reg = <0x0 0x2060000 0x0 0x100>;
1803 #size-cells = <0>;
1805 clocks = <&k3_clks 193 0>;
1812 reg = <0x0 0x4e80000 0x0 0x100>;
1823 reg = <0x0 0x4e84000 0x0 0x10000>;
1826 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1838 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
1839 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
1851 #size-cells = <0>;
1853 port@0 {
1854 reg = <0>;
1866 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1867 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1868 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1869 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1871 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1872 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1873 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1874 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1876 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1877 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1878 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1879 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1881 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1882 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1883 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1884 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1885 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1894 clocks = <&k3_clks 152 0>,
1918 reg = <0x0 0x02b00000 0x0 0x2000>,
1919 <0x0 0x02b08000 0x0 0x1000>;
1925 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1936 reg = <0x0 0x02b10000 0x0 0x2000>,
1937 <0x0 0x02b18000 0x0 0x1000>;
1943 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1954 reg = <0x0 0x02b20000 0x0 0x2000>,
1955 <0x0 0x02b28000 0x0 0x1000>;
1961 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1972 reg = <0x0 0x02b30000 0x0 0x2000>,
1973 <0x0 0x02b38000 0x0 0x1000>;
1979 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1990 reg = <0x0 0x02b40000 0x0 0x2000>,
1991 <0x0 0x02b48000 0x0 0x1000>;
1997 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
2008 reg = <0x0 0x02b50000 0x0 0x2000>,
2009 <0x0 0x02b58000 0x0 0x1000>;
2015 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
2026 reg = <0x0 0x02b60000 0x0 0x2000>,
2027 <0x0 0x02b68000 0x0 0x1000>;
2033 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
2044 reg = <0x0 0x02b70000 0x0 0x2000>,
2045 <0x0 0x02b78000 0x0 0x1000>;
2051 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
2062 reg = <0x0 0x02b80000 0x0 0x2000>,
2063 <0x0 0x02b88000 0x0 0x1000>;
2069 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
2080 reg = <0x0 0x02b90000 0x0 0x2000>,
2081 <0x0 0x02b98000 0x0 0x1000>;
2087 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
2098 reg = <0x0 0x02ba0000 0x0 0x2000>,
2099 <0x0 0x02ba8000 0x0 0x1000>;
2105 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
2116 reg = <0x0 0x02bb0000 0x0 0x2000>,
2117 <0x0 0x02bb8000 0x0 0x1000>;
2123 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
2134 reg = <0x0 0x2200000 0x0 0x100>;
2143 reg = <0x0 0x2210000 0x0 0x100>;
2155 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
2156 <0x5d00000 0x00 0x5d00000 0x20000>;
2161 reg = <0x5c00000 0x00008000>,
2162 <0x5c10000 0x00008000>;
2166 ti,sci-proc-ids = <0x06 0xff>;
2176 reg = <0x5d00000 0x00008000>,
2177 <0x5d10000 0x00008000>;
2181 ti,sci-proc-ids = <0x07 0xff>;
2195 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
2196 <0x5f00000 0x00 0x5f00000 0x20000>;
2201 reg = <0x5e00000 0x00008000>,
2202 <0x5e10000 0x00008000>;
2206 ti,sci-proc-ids = <0x08 0xff>;
2216 reg = <0x5f00000 0x00008000>,
2217 <0x5f10000 0x00008000>;
2221 ti,sci-proc-ids = <0x09 0xff>;
2232 reg = <0x4d 0x80800000 0x00 0x00048000>,
2233 <0x4d 0x80e00000 0x00 0x00008000>,
2234 <0x4d 0x80f00000 0x00 0x00008000>;
2238 ti,sci-proc-ids = <0x03 0xff>;
2246 reg = <0x4d 0x81800000 0x00 0x00048000>,
2247 <0x4d 0x81e00000 0x00 0x00008000>,
2248 <0x4d 0x81f00000 0x00 0x00008000>;
2252 ti,sci-proc-ids = <0x04 0xff>;
2260 reg = <0x00 0x64800000 0x00 0x00080000>,
2261 <0x00 0x64e00000 0x00 0x0000c000>;
2265 ti,sci-proc-ids = <0x30 0xff>;
2273 reg = <0x00 0xb000000 0x00 0x80000>;
2277 ranges = <0x0 0x00 0x0b000000 0x100000>;
2279 icssg0_mem: memories@0 {
2280 reg = <0x0 0x2000>,
2281 <0x2000 0x2000>,
2282 <0x10000 0x10000>;
2289 reg = <0x26000 0x200>;
2292 ranges = <0x0 0x26000 0x2000>;
2296 #size-cells = <0>;
2299 reg = <0x3c>;
2300 #clock-cells = <0>;
2308 reg = <0x30>;
2309 #clock-cells = <0>;
2320 reg = <0x32000 0x100>;
2325 reg = <0x33000 0x1000>;
2330 reg = <0x20000 0x2000>;
2349 reg = <0x34000 0x3000>,
2350 <0x22000 0x100>,
2351 <0x22400 0x100>;
2358 reg = <0x4000 0x2000>,
2359 <0x23000 0x100>,
2360 <0x23400 0x100>;
2367 reg = <0xa000 0x1800>,
2368 <0x25000 0x100>,
2369 <0x25400 0x100>;
2376 reg = <0x38000 0x3000>,
2377 <0x24000 0x100>,
2378 <0x24400 0x100>;
2385 reg = <0x6000 0x2000>,
2386 <0x23800 0x100>,
2387 <0x23c00 0x100>;
2394 reg = <0xc000 0x1800>,
2395 <0x25800 0x100>,
2396 <0x25c00 0x100>;
2403 reg = <0x32400 0x100>;
2407 #size-cells = <0>;
2415 reg = <0x00 0xb100000 0x00 0x80000>;
2419 ranges = <0x0 0x00 0x0b100000 0x100000>;
2422 reg = <0x0 0x2000>,
2423 <0x2000 0x2000>,
2424 <0x10000 0x10000>;
2431 reg = <0x26000 0x200>;
2434 ranges = <0x0 0x26000 0x2000>;
2438 #size-cells = <0>;
2441 reg = <0x3c>;
2442 #clock-cells = <0>;
2450 reg = <0x30>;
2451 #clock-cells = <0>;
2462 reg = <0x32000 0x100>;
2467 reg = <0x33000 0x1000>;
2472 reg = <0x20000 0x2000>;
2491 reg = <0x34000 0x4000>,
2492 <0x22000 0x100>,
2493 <0x22400 0x100>;
2500 reg = <0x4000 0x2000>,
2501 <0x23000 0x100>,
2502 <0x23400 0x100>;
2509 reg = <0xa000 0x1800>,
2510 <0x25000 0x100>,
2511 <0x25400 0x100>;
2518 reg = <0x38000 0x4000>,
2519 <0x24000 0x100>,
2520 <0x24400 0x100>;
2527 reg = <0x6000 0x2000>,
2528 <0x23800 0x100>,
2529 <0x23c00 0x100>;
2536 reg = <0xc000 0x1800>,
2537 <0x25800 0x100>,
2538 <0x25c00 0x100>;
2545 reg = <0x32400 0x100>;
2549 #size-cells = <0>;
2557 reg = <0x00 0x02701000 0x00 0x200>,
2558 <0x00 0x02708000 0x00 0x8000>;
2561 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
2566 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2572 reg = <0x00 0x02711000 0x00 0x200>,
2573 <0x00 0x02718000 0x00 0x8000>;
2576 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
2581 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2587 reg = <0x00 0x02721000 0x00 0x200>,
2588 <0x00 0x02728000 0x00 0x8000>;
2591 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
2596 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2602 reg = <0x00 0x02731000 0x00 0x200>,
2603 <0x00 0x02738000 0x00 0x8000>;
2606 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
2611 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2617 reg = <0x00 0x02741000 0x00 0x200>,
2618 <0x00 0x02748000 0x00 0x8000>;
2621 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
2626 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2632 reg = <0x00 0x02751000 0x00 0x200>,
2633 <0x00 0x02758000 0x00 0x8000>;
2636 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
2641 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2647 reg = <0x00 0x02761000 0x00 0x200>,
2648 <0x00 0x02768000 0x00 0x8000>;
2651 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
2656 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2662 reg = <0x00 0x02771000 0x00 0x200>,
2663 <0x00 0x02778000 0x00 0x8000>;
2666 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
2671 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2677 reg = <0x00 0x02781000 0x00 0x200>,
2678 <0x00 0x02788000 0x00 0x8000>;
2681 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
2686 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2692 reg = <0x00 0x02791000 0x00 0x200>,
2693 <0x00 0x02798000 0x00 0x8000>;
2696 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
2701 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2707 reg = <0x00 0x027a1000 0x00 0x200>,
2708 <0x00 0x027a8000 0x00 0x8000>;
2711 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
2716 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2722 reg = <0x00 0x027b1000 0x00 0x200>,
2723 <0x00 0x027b8000 0x00 0x8000>;
2726 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
2731 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2737 reg = <0x00 0x027c1000 0x00 0x200>,
2738 <0x00 0x027c8000 0x00 0x8000>;
2741 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
2746 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2752 reg = <0x00 0x027d1000 0x00 0x200>,
2753 <0x00 0x027d8000 0x00 0x8000>;
2756 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
2761 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2767 reg = <0x00 0x02100000 0x00 0x400>;
2770 #size-cells = <0>;
2778 reg = <0x00 0x02110000 0x00 0x400>;
2781 #size-cells = <0>;
2789 reg = <0x00 0x02120000 0x00 0x400>;
2792 #size-cells = <0>;
2800 reg = <0x00 0x02130000 0x00 0x400>;
2803 #size-cells = <0>;
2811 reg = <0x00 0x02140000 0x00 0x400>;
2814 #size-cells = <0>;
2822 reg = <0x00 0x02150000 0x00 0x400>;
2825 #size-cells = <0>;
2833 reg = <0x00 0x02160000 0x00 0x400>;
2836 #size-cells = <0>;
2844 reg = <0x00 0x02170000 0x00 0x400>;
2847 #size-cells = <0>;
2855 reg = <0x0 0x700000 0x0 0x1000>;