Lines Matching +full:single +full:- +full:board
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with
4 * J721E board.
6 * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM
8 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/net/ti-dp83867.h>
17 #include "k3-pinctrl.h"
21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
22 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
23 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
24 ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
30 pinctrl-names = "default";
31 pinctrl-0 = <&rgmii1_default_pins
39 phy-handle = <&cpsw9g_phy12>;
40 phy-mode = "rgmii-rxid";
41 mac-address = [00 00 00 00 00 00];
47 phy-handle = <&cpsw9g_phy15>;
48 phy-mode = "rgmii-rxid";
49 mac-address = [00 00 00 00 00 00];
55 phy-handle = <&cpsw9g_phy0>;
56 phy-mode = "rgmii-rxid";
57 mac-address = [00 00 00 00 00 00];
63 phy-handle = <&cpsw9g_phy3>;
64 phy-mode = "rgmii-rxid";
65 mac-address = [00 00 00 00 00 00];
71 pinctrl-names = "default";
72 pinctrl-0 = <&mdio0_default_pins>;
74 #address-cells = <1>;
75 #size-cells = <0>;
77 cpsw9g_phy0: ethernet-phy@0 {
79 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
80 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
81 ti,min-output-impedance;
83 cpsw9g_phy3: ethernet-phy@3 {
85 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
86 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
87 ti,min-output-impedance;
89 cpsw9g_phy12: ethernet-phy@12 {
91 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
92 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
93 ti,min-output-impedance;
95 cpsw9g_phy15: ethernet-phy@15 {
97 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
98 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
99 ti,min-output-impedance;
104 p15-hog {
105 /* P15 - EXP_MUX2 */
106 gpio-hog;
108 output-high;
109 line-name = "EXP_MUX2";
112 p16-hog {
113 /* P16 - EXP_MUX3 */
114 gpio-hog;
116 output-high;
117 line-name = "EXP_MUX3";
122 mdio0_default_pins: mdio0-default-pins {
123 pinctrl-single,pins = <
129 rgmii1_default_pins: rgmii1-default-pins {
130 pinctrl-single,pins = <
146 rgmii2_default_pins: rgmii2-default-pins {
147 pinctrl-single,pins = <
163 rgmii3_default_pins: rgmii3-default-pins {
164 pinctrl-single,pins = <
180 rgmii4_default_pins: rgmii4-default-pins {
181 pinctrl-single,pins = <