Lines Matching +full:vdd2 +full:- +full:supply
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721e-som-p0.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/net/ti-dp83867.h>
14 #include <dt-bindings/phy/phy-cadence.h>
17 compatible = "ti,j721e-evm", "ti,j721e";
33 stdout-path = "serial2:115200n8";
36 gpio_keys: gpio-keys {
37 compatible = "gpio-keys";
39 pinctrl-names = "default";
40 pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>;
42 sw10: switch-10 {
48 sw11: switch-11 {
55 evm_12v0: fixedregulator-evm12v0 {
56 /* main supply */
57 compatible = "regulator-fixed";
58 regulator-name = "evm_12v0";
59 regulator-min-microvolt = <12000000>;
60 regulator-max-microvolt = <12000000>;
61 regulator-always-on;
62 regulator-boot-on;
65 vsys_3v3: fixedregulator-vsys3v3 {
67 compatible = "regulator-fixed";
68 regulator-name = "vsys_3v3";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 vin-supply = <&evm_12v0>;
72 regulator-always-on;
73 regulator-boot-on;
76 vsys_5v0: fixedregulator-vsys5v0 {
78 compatible = "regulator-fixed";
79 regulator-name = "vsys_5v0";
80 regulator-min-microvolt = <5000000>;
81 regulator-max-microvolt = <5000000>;
82 vin-supply = <&evm_12v0>;
83 regulator-always-on;
84 regulator-boot-on;
87 vdd_mmc1: fixedregulator-sd {
88 compatible = "regulator-fixed";
89 regulator-name = "vdd_mmc1";
90 regulator-min-microvolt = <3300000>;
91 regulator-max-microvolt = <3300000>;
92 regulator-boot-on;
93 enable-active-high;
94 vin-supply = <&vsys_3v3>;
98 vdd_sd_dv_alt: gpio-regulator-TLV71033 {
99 compatible = "regulator-gpio";
100 pinctrl-names = "default";
101 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
102 regulator-name = "tlv71033";
103 regulator-min-microvolt = <1800000>;
104 regulator-max-microvolt = <3300000>;
105 regulator-boot-on;
106 vin-supply = <&vsys_5v0>;
112 sound0: sound-0 {
113 compatible = "ti,j721e-cpb-audio";
114 model = "j721e-cpb";
116 ti,cpb-mcasp = <&mcasp10>;
117 ti,cpb-codec = <&pcm3168a_1>;
123 clock-names = "cpb-mcasp-auxclk",
124 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
125 "cpb-codec-scki",
126 "cpb-codec-scki-48000", "cpb-codec-scki-44100";
129 transceiver1: can-phy0 {
131 #phy-cells = <0>;
132 max-bitrate = <5000000>;
133 pinctrl-names = "default";
134 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
135 standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>;
136 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
139 transceiver2: can-phy1 {
141 #phy-cells = <0>;
142 max-bitrate = <5000000>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
145 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
148 transceiver3: can-phy2 {
150 #phy-cells = <0>;
151 max-bitrate = <5000000>;
152 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
153 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
156 transceiver4: can-phy3 {
158 #phy-cells = <0>;
159 max-bitrate = <5000000>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&main_mcan2_gpio_pins_default>;
162 standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
165 dp_pwr_3v3: regulator-dp-pwr {
166 compatible = "regulator-fixed";
167 regulator-name = "dp-pwr";
168 regulator-min-microvolt = <3300000>;
169 regulator-max-microvolt = <3300000>;
170 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */
171 enable-active-high;
175 compatible = "dp-connector";
177 type = "full-size";
178 dp-pwr-supply = <&dp_pwr_3v3>;
182 remote-endpoint = <&dp0_out>;
189 main_uart0_pins_default: main-uart0-default-pins {
190 pinctrl-single,pins = <
198 main_uart1_pins_default: main-uart1-default-pins {
199 pinctrl-single,pins = <
205 main_uart2_pins_default: main-uart2-default-pins {
206 pinctrl-single,pins = <
212 main_uart4_pins_default: main-uart4-default-pins {
213 pinctrl-single,pins = <
219 sw10_button_pins_default: sw10-button-default-pins {
220 pinctrl-single,pins = <
225 main_mmc1_pins_default: main-mmc1-default-pins {
226 pinctrl-single,pins = <
239 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
240 pinctrl-single,pins = <
245 main_usbss0_pins_default: main-usbss0-default-pins {
246 pinctrl-single,pins = <
252 main_usbss1_pins_default: main-usbss1-default-pins {
253 pinctrl-single,pins = <
258 dp0_pins_default: dp0-default-pins {
259 pinctrl-single,pins = <
264 main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins {
265 pinctrl-single,pins = <
270 main_i2c0_pins_default: main-i2c0-default-pins {
271 pinctrl-single,pins = <
277 main_i2c1_pins_default: main-i2c1-default-pins {
278 pinctrl-single,pins = <
284 main_i2c3_pins_default: main-i2c3-default-pins {
285 pinctrl-single,pins = <
291 main_i2c6_pins_default: main-i2c6-default-pins {
292 pinctrl-single,pins = <
298 mcasp10_pins_default: mcasp10-default-pins {
299 pinctrl-single,pins = <
312 audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins {
313 pinctrl-single,pins = <
318 main_mcan0_pins_default: main-mcan0-default-pins {
319 pinctrl-single,pins = <
325 main_mcan2_pins_default: main-mcan2-default-pins {
326 pinctrl-single,pins = <
332 main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins {
333 pinctrl-single,pins = <
340 wkup_uart0_pins_default: wkup-uart0-default-pins {
341 pinctrl-single,pins = <
347 mcu_uart0_pins_default: mcu-uart0-default-pins {
348 pinctrl-single,pins = <
356 sw11_button_pins_default: sw11-button-default-pins {
357 pinctrl-single,pins = <
362 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
363 pinctrl-single,pins = <
375 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
376 pinctrl-single,pins = <
392 mcu_mdio_pins_default: mcu-mdio1-default-pins {
393 pinctrl-single,pins = <
399 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
400 pinctrl-single,pins = <
406 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
407 pinctrl-single,pins = <
413 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
414 pinctrl-single,pins = <
420 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
421 pinctrl-single,pins = <
426 wkup_gpio_pins_default: wkup-gpio-default-pins {
427 pinctrl-single,pins = <
436 pinctrl-names = "default";
437 pinctrl-0 = <&wkup_uart0_pins_default>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&mcu_uart0_pins_default>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&main_uart0_pins_default>;
451 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
456 pinctrl-names = "default";
457 pinctrl-0 = <&main_uart1_pins_default>;
462 pinctrl-names = "default";
463 pinctrl-0 = <&main_uart2_pins_default>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&main_uart4_pins_default>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&wkup_gpio_pins_default>;
489 non-removable;
490 ti,driver-strength-ohm = <50>;
491 disable-wp;
497 vmmc-supply = <&vdd_mmc1>;
498 vqmmc-supply = <&vdd_sd_dv_alt>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&main_mmc1_pins_default>;
501 ti,driver-strength-ohm = <50>;
502 disable-wp;
506 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
510 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
519 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
520 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
526 cdns,num-lanes = <2>;
527 #phy-cells = <0>;
528 cdns,phy-type = <PHY_TYPE_USB3>;
534 pinctrl-names = "default";
535 pinctrl-0 = <&main_usbss0_pins_default>;
536 ti,vbus-divider;
541 maximum-speed = "super-speed";
543 phy-names = "cdns3,usb3-phy";
547 pinctrl-names = "default";
548 pinctrl-0 = <&main_usbss1_pins_default>;
549 ti,usb2-only;
554 maximum-speed = "high-speed";
558 pinctrl-names = "default";
559 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
562 compatible = "jedec,spi-nor";
564 spi-tx-bus-width = <1>;
565 spi-rx-bus-width = <4>;
566 spi-max-frequency = <40000000>;
567 cdns,tshsl-ns = <60>;
568 cdns,tsd2d-ns = <60>;
569 cdns,tchsh-ns = <60>;
570 cdns,tslch-ns = <60>;
571 cdns,read-delay = <2>;
574 compatible = "fixed-partitions";
575 #address-cells = <1>;
576 #size-cells = <1>;
589 label = "qspi.u-boot";
624 ti,adc-channels = <0 1 2 3 4 5 6 7>;
631 ti,adc-channels = <0 1 2 3 4 5 6 7>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&main_i2c0_pins_default>;
639 clock-frequency = <400000>;
644 gpio-controller;
645 #gpio-cells = <2>;
651 gpio-controller;
652 #gpio-cells = <2>;
654 p09-hog {
655 /* P11 - MCASP/TRACE_MUX_S0 */
656 gpio-hog;
658 output-low;
659 line-name = "MCASP/TRACE_MUX_S0";
662 p10-hog {
663 /* P12 - MCASP/TRACE_MUX_S1 */
664 gpio-hog;
666 output-high;
667 line-name = "MCASP/TRACE_MUX_S1";
674 pinctrl-names = "default";
675 pinctrl-0 = <&main_i2c1_pins_default>;
676 clock-frequency = <400000>;
681 gpio-controller;
682 #gpio-cells = <2>;
683 pinctrl-names = "default";
684 pinctrl-0 = <&main_i2c1_exp4_pins_default>;
685 interrupt-parent = <&main_gpio1>;
687 interrupt-controller;
688 #interrupt-cells = <2>;
694 pinctrl-names = "default";
695 pinctrl-0 = <&audi_ext_refclk2_pins_default>;
700 pinctrl-names = "default";
701 pinctrl-0 = <&main_i2c3_pins_default>;
702 clock-frequency = <400000>;
707 gpio-controller;
708 #gpio-cells = <2>;
711 pcm3168a_1: audio-codec@44 {
715 #sound-dai-cells = <1>;
717 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
719 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
721 clock-names = "scki";
723 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
724 assigned-clocks = <&k3_clks 157 371>;
725 assigned-clock-parents = <&k3_clks 157 400>;
726 assigned-clock-rates = <24576000>; /* for 48KHz */
728 VDD1-supply = <&vsys_3v3>;
729 VDD2-supply = <&vsys_3v3>;
730 VCCAD1-supply = <&vsys_5v0>;
731 VCCAD2-supply = <&vsys_5v0>;
732 VCCDA1-supply = <&vsys_5v0>;
733 VCCDA2-supply = <&vsys_5v0>;
739 pinctrl-names = "default";
740 pinctrl-0 = <&main_i2c6_pins_default>;
741 clock-frequency = <400000>;
746 gpio-controller;
747 #gpio-cells = <2>;
752 pinctrl-names = "default";
753 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
757 phy0: ethernet-phy@0 {
759 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
760 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
765 phy-mode = "rgmii-rxid";
766 phy-handle = <&phy0>;
773 * VP0 - DisplayPort SST
774 * VP1 - DPI0
775 * VP2 - DSI
776 * VP3 - DPI1
779 assigned-clocks = <&k3_clks 152 1>,
783 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
792 remote-endpoint = <&dp0_in>;
798 #address-cells = <1>;
799 #size-cells = <0>;
804 remote-endpoint = <&dpi0_out>;
811 remote-endpoint = <&dp_connector_in>;
818 #sound-dai-cells = <0>;
820 pinctrl-names = "default";
821 pinctrl-0 = <&mcasp10_pins_default>;
823 op-mode = <0>; /* MCASP_IIS_MODE */
824 tdm-slots = <2>;
825 auxclk-fs-ratio = <256>;
827 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
831 tx-num-evt = <0>;
832 rx-num-evt = <0>;
836 clock-frequency = <100000000>;
840 assigned-clocks = <&wiz0_pll1_refclk>;
841 assigned-clock-parents = <&cmn_refclk1>;
845 assigned-clocks = <&wiz0_refclk_dig>;
846 assigned-clock-parents = <&cmn_refclk1>;
850 assigned-clocks = <&wiz1_pll1_refclk>;
851 assigned-clock-parents = <&cmn_refclk1>;
855 assigned-clocks = <&wiz1_refclk_dig>;
856 assigned-clock-parents = <&cmn_refclk1>;
860 assigned-clocks = <&wiz2_pll1_refclk>;
861 assigned-clock-parents = <&cmn_refclk1>;
865 assigned-clocks = <&wiz2_refclk_dig>;
866 assigned-clock-parents = <&cmn_refclk1>;
870 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
871 assigned-clock-parents = <&wiz0_pll1_refclk>;
875 cdns,num-lanes = <1>;
876 #phy-cells = <0>;
877 cdns,phy-type = <PHY_TYPE_PCIE>;
883 assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
884 assigned-clock-parents = <&wiz1_pll1_refclk>;
888 cdns,num-lanes = <2>;
889 #phy-cells = <0>;
890 cdns,phy-type = <PHY_TYPE_PCIE>;
896 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
897 assigned-clock-parents = <&wiz2_pll1_refclk>;
901 cdns,num-lanes = <2>;
902 #phy-cells = <0>;
903 cdns,phy-type = <PHY_TYPE_PCIE>;
912 cdns,phy-type = <PHY_TYPE_DP>;
913 cdns,num-lanes = <4>;
914 cdns,max-bit-rate = <5400>;
915 #phy-cells = <0>;
921 phy-names = "dpphy";
922 pinctrl-names = "default";
923 pinctrl-0 = <&dp0_pins_default>;
928 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
930 phy-names = "pcie-phy";
931 num-lanes = <1>;
936 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
938 phy-names = "pcie-phy";
939 num-lanes = <2>;
944 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
946 phy-names = "pcie-phy";
947 num-lanes = <2>;
952 pinctrl-names = "default";
953 pinctrl-0 = <&mcu_mcan0_pins_default>;
959 pinctrl-names = "default";
960 pinctrl-0 = <&mcu_mcan1_pins_default>;
966 pinctrl-names = "default";
967 pinctrl-0 = <&main_mcan0_pins_default>;
973 pinctrl-names = "default";
974 pinctrl-0 = <&main_mcan2_pins_default>;