Lines Matching +full:- +full:10
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Infotainment Expansion Board for j721e-evm
6 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
15 #include "k3-pinctrl.h"
18 hdmi-connector {
19 compatible = "hdmi-connector";
22 ddc-i2c-bus = <&main_i2c1>;
24 /* P12 - HDMI_HPD */
25 hpd-gpios = <&exp6 10 GPIO_ACTIVE_HIGH>;
29 remote-endpoint = <&tfp410_out>;
34 dvi-bridge {
35 #address-cells = <1>;
36 #size-cells = <0>;
38 /* P10 - HDMI_PDn */
39 powerdown-gpios = <&exp6 8 GPIO_ACTIVE_LOW>;
45 remote-endpoint = <&dpi_out0>;
46 pclk-sample = <1>;
54 remote-endpoint =
62 main_i2c1_exp6_pins_default: main-i2c1-exp6-default-pins {
63 pinctrl-single,pins = <
68 dss_vout0_pins_default: dss-vout0-default-pins {
69 pinctrl-single,pins = <
70 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
71 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
72 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */
73 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */
74 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */
75 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */
76 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */
77 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */
78 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */
79 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */
80 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */
81 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */
82 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */
83 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */
84 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */
85 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */
86 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */
87 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */
88 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */
89 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */
90 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */
91 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */
92 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */
93 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */
94 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */
95 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */
96 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */
97 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */
103 p14-hog {
104 /* P14 - VINOUT_MUX_SEL0 */
105 gpio-hog;
107 output-low;
108 line-name = "VINOUT_MUX_SEL0";
111 p15-hog {
112 /* P15 - VINOUT_MUX_SEL1 */
113 gpio-hog;
115 output-high;
116 line-name = "VINOUT_MUX_SEL1";
122 clock-frequency = <100000>;
123 #address-cells = <1>;
124 #size-cells = <0>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&main_i2c1_exp6_pins_default>;
133 interrupt-parent = <&main_gpio1>;
135 interrupt-controller;
136 #interrupt-cells = <2>;
138 p11-hog {
139 /* P11 - HDMI_DDC_OE */
140 gpio-hog;
142 output-high;
143 line-name = "HDMI_DDC_OE";
149 pinctrl-names = "default";
150 pinctrl-0 = <&dss_vout0_pins_default>;
154 #address-cells = <1>;
155 #size-cells = <0>;
161 remote-endpoint = <&tfp410_in>;