Lines Matching +full:pmu +full:- +full:sram

1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5  * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/soc/ti,sci_pm_domain.h>
12 #include "k3-pinctrl.h"
17 	interrupt-parent = <&gic500>;
18 	#address-cells = <2>;
19 	#size-cells = <2>;
24 		#address-cells = <1>;
25 		#size-cells = <0>;
26 		cpu-map {
40 			compatible = "arm,cortex-a72";
43 			enable-method = "psci";
44 			i-cache-size = <0xc000>;
45 			i-cache-line-size = <64>;
46 			i-cache-sets = <256>;
47 			d-cache-size = <0x8000>;
48 			d-cache-line-size = <64>;
49 			d-cache-sets = <256>;
50 			next-level-cache = <&L2_0>;
54 			compatible = "arm,cortex-a72";
57 			enable-method = "psci";
58 			i-cache-size = <0xc000>;
59 			i-cache-line-size = <64>;
60 			i-cache-sets = <256>;
61 			d-cache-size = <0x8000>;
62 			d-cache-line-size = <64>;
63 			d-cache-sets = <256>;
64 			next-level-cache = <&L2_0>;
68 	L2_0: l2-cache0 {
70 		cache-level = <2>;
71 		cache-unified;
72 		cache-size = <0x100000>;
73 		cache-line-size = <64>;
74 		cache-sets = <1024>;
75 		next-level-cache = <&msmc_l3>;
78 	msmc_l3: l3-cache0 {
80 		cache-level = <3>;
81 		cache-unified;
86 			compatible = "linaro,optee-tz";
91 			compatible = "arm,psci-1.0";
96 	a72_timer0: timer-cl0-cpu0 {
97 		compatible = "arm,armv8-timer";
104 	pmu: pmu {  label
105 		compatible = "arm,cortex-a72-pmu";
110 		compatible = "simple-bus";
111 		#address-cells = <2>;
112 		#size-cells = <2>;
140 			compatible = "simple-bus";
141 			#address-cells = <2>;
142 			#size-cells = <2>;
148 				 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
159 	#include "k3-j7200-thermal.dtsi"
163 #include "k3-j7200-main.dtsi"
164 #include "k3-j7200-mcu-wakeup.dtsi"