Lines Matching +full:am654 +full:- +full:vtm
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
26 k3_clks: clock-controller {
27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
33 #reset-cells = <2>;
39 compatible = "ti,am654-timer";
43 clock-names = "fck";
44 assigned-clocks = <&k3_clks 35 1>;
45 assigned-clock-parents = <&k3_clks 35 2>;
46 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
47 ti,timer-pwm;
52 compatible = "ti,am654-timer";
56 clock-names = "fck";
57 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
58 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
59 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
60 ti,timer-pwm;
65 compatible = "ti,am654-timer";
69 clock-names = "fck";
70 assigned-clocks = <&k3_clks 72 1>;
71 assigned-clock-parents = <&k3_clks 72 2>;
72 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
73 ti,timer-pwm;
78 compatible = "ti,am654-timer";
82 clock-names = "fck";
83 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
84 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>;
85 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
86 ti,timer-pwm;
91 compatible = "ti,am654-timer";
95 clock-names = "fck";
96 assigned-clocks = <&k3_clks 74 1>;
97 assigned-clock-parents = <&k3_clks 74 2>;
98 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
99 ti,timer-pwm;
104 compatible = "ti,am654-timer";
108 clock-names = "fck";
109 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
110 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>;
111 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
112 ti,timer-pwm;
117 compatible = "ti,am654-timer";
121 clock-names = "fck";
122 assigned-clocks = <&k3_clks 76 1>;
123 assigned-clock-parents = <&k3_clks 76 2>;
124 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
125 ti,timer-pwm;
130 compatible = "ti,am654-timer";
134 clock-names = "fck";
135 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>;
136 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>;
137 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
138 ti,timer-pwm;
143 compatible = "ti,am654-timer";
147 clock-names = "fck";
148 assigned-clocks = <&k3_clks 78 1>;
149 assigned-clock-parents = <&k3_clks 78 2>;
150 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
151 ti,timer-pwm;
156 compatible = "ti,am654-timer";
160 clock-names = "fck";
161 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>;
162 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>;
163 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
164 ti,timer-pwm;
168 compatible = "simple-bus";
169 #address-cells = <1>;
170 #size-cells = <1>;
173 cpsw_mac_syscon: ethernet-mac-syscon@200 {
174 compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
179 compatible = "ti,am654-phy-gmii-sel";
181 #phy-cells = <1>;
186 compatible = "simple-bus";
187 #address-cells = <1>;
188 #size-cells = <1>;
192 compatible = "ti,am654-chipid";
199 compatible = "ti,j7200-padconf", "pinctrl-single";
201 #pinctrl-cells = <1>;
202 pinctrl-single,register-width = <32>;
203 pinctrl-single,function-mask = <0x0000000F>;
209 compatible = "ti,j7200-padconf", "pinctrl-single";
211 #pinctrl-cells = <1>;
212 pinctrl-single,register-width = <32>;
213 pinctrl-single,function-mask = <0x0000000F>;
218 compatible = "ti,j7200-padconf", "pinctrl-single";
221 #pinctrl-cells = <1>;
222 pinctrl-single,register-width = <32>;
223 pinctrl-single,function-mask = <0xffffffff>;
227 compatible = "ti,j7200-padconf", "pinctrl-single";
230 #pinctrl-cells = <1>;
231 pinctrl-single,register-width = <32>;
232 pinctrl-single,function-mask = <0xffffffff>;
236 compatible = "ti,j7200-padconf", "pinctrl-single";
239 #pinctrl-cells = <1>;
240 pinctrl-single,register-width = <32>;
241 pinctrl-single,function-mask = <0xffffffff>;
245 compatible = "ti,j7200-padconf", "pinctrl-single";
248 #pinctrl-cells = <1>;
249 pinctrl-single,register-width = <32>;
250 pinctrl-single,function-mask = <0xffffffff>;
254 compatible = "mmio-sram";
257 #address-cells = <1>;
258 #size-cells = <1>;
262 compatible = "ti,j721e-uart", "ti,am654-uart";
265 clock-frequency = <48000000>;
266 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
268 clock-names = "fclk";
273 compatible = "ti,j721e-uart", "ti,am654-uart";
276 clock-frequency = <96000000>;
277 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
279 clock-names = "fclk";
283 wkup_gpio_intr: interrupt-controller@42200000 {
284 compatible = "ti,sci-intr";
286 ti,intr-trigger-type = <1>;
287 interrupt-controller;
288 interrupt-parent = <&gic500>;
289 #interrupt-cells = <1>;
291 ti,sci-dev-id = <137>;
292 ti,interrupt-ranges = <16 960 16>;
296 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
298 gpio-controller;
299 #gpio-cells = <2>;
300 interrupt-parent = <&wkup_gpio_intr>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
305 ti,davinci-gpio-unbanked = <0>;
306 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
308 clock-names = "gpio";
313 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
315 gpio-controller;
316 #gpio-cells = <2>;
317 interrupt-parent = <&wkup_gpio_intr>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
322 ti,davinci-gpio-unbanked = <0>;
323 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
325 clock-names = "gpio";
330 compatible = "simple-bus";
331 #address-cells = <2>;
332 #size-cells = <2>;
334 dma-coherent;
335 dma-ranges;
336 ti,sci-dev-id = <232>;
339 compatible = "ti,am654-navss-ringacc";
345 reg-names = "rt", "fifos", "proxy_gcfg",
347 ti,num-rings = <286>;
348 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
350 ti,sci-dev-id = <235>;
351 msi-parent = <&main_udmass_inta>;
354 mcu_udmap: dma-controller@285c0000 {
355 compatible = "ti,j721e-navss-mcu-udmap";
362 reg-names = "gcfg", "rchanrt", "tchanrt",
364 msi-parent = <&main_udmass_inta>;
365 #dma-cells = <1>;
368 ti,sci-dev-id = <236>;
371 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
373 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
375 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
380 compatible = "ti,am654-secure-proxy";
381 #mbox-cells = <1>;
382 reg-names = "target_data", "rt", "scfg";
389 * firmware on non-MPU processors
395 compatible = "ti,j721e-cpsw-nuss";
396 #address-cells = <2>;
397 #size-cells = <2>;
399 reg-names = "cpsw_nuss";
401 dma-coherent;
403 clock-names = "fck";
404 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
415 dma-names = "tx0", "tx1", "tx2", "tx3",
419 ethernet-ports {
420 #address-cells = <1>;
421 #size-cells = <0>;
425 ti,mac-only;
427 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
433 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
435 #address-cells = <1>;
436 #size-cells = <0>;
438 clock-names = "fck";
443 compatible = "ti,am65-cpts";
446 clock-names = "cpts";
447 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
448 interrupt-names = "cpts";
449 ti,cpts-ext-ts-inputs = <4>;
450 ti,cpts-periodic-outputs = <2>;
455 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
458 #address-cells = <1>;
459 #size-cells = <0>;
460 clock-names = "fck";
462 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
467 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
470 #address-cells = <1>;
471 #size-cells = <0>;
472 clock-names = "fck";
474 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
479 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
482 #address-cells = <1>;
483 #size-cells = <0>;
484 clock-names = "fck";
486 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
491 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
494 #address-cells = <1>;
495 #size-cells = <0>;
496 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
502 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
505 #address-cells = <1>;
506 #size-cells = <0>;
507 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
513 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
516 #address-cells = <1>;
517 #size-cells = <0>;
518 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
524 compatible = "simple-bus";
525 #address-cells = <2>;
526 #size-cells = <2>;
532 hbmc_mux: mux-controller@47000004 {
533 compatible = "reg-mux";
535 #mux-control-cells = <1>;
536 mux-reg-masks = <0x0 0x2>; /* HBMC select */
540 compatible = "ti,am654-hbmc";
543 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
545 assigned-clocks = <&k3_clks 102 5>;
546 assigned-clock-rates = <333333333>;
547 #address-cells = <2>;
548 #size-cells = <1>;
549 mux-controls = <&hbmc_mux 0>;
553 compatible = "ti,am654-ospi", "cdns,qspi-nor";
557 cdns,fifo-depth = <256>;
558 cdns,fifo-width = <4>;
559 cdns,trigger-address = <0x0>;
561 assigned-clocks = <&k3_clks 103 0>;
562 assigned-clock-parents = <&k3_clks 103 2>;
563 assigned-clock-rates = <166666666>;
564 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
565 #address-cells = <1>;
566 #size-cells = <0>;
572 compatible = "ti,am3359-tscadc";
575 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
577 assigned-clocks = <&k3_clks 0 3>;
578 assigned-clock-rates = <60000000>;
579 clock-names = "fck";
582 dma-names = "fifo0", "fifo1";
585 #io-channel-cells = <1>;
586 compatible = "ti,am3359-adc";
591 compatible = "ti,j7200-r5fss";
592 ti,cluster-mode = <1>;
593 #address-cells = <1>;
594 #size-cells = <1>;
597 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
600 compatible = "ti,j7200-r5f";
603 reg-names = "atcm", "btcm";
605 ti,sci-dev-id = <250>;
606 ti,sci-proc-ids = <0x01 0xff>;
608 firmware-name = "j7200-mcu-r5f0_0-fw";
609 ti,atcm-enable = <1>;
610 ti,btcm-enable = <1>;
615 compatible = "ti,j7200-r5f";
618 reg-names = "atcm", "btcm";
620 ti,sci-dev-id = <251>;
621 ti,sci-proc-ids = <0x02 0xff>;
623 firmware-name = "j7200-mcu-r5f0_1-fw";
624 ti,atcm-enable = <1>;
625 ti,btcm-enable = <1>;
631 compatible = "ti,j721e-sa2ul";
633 power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
634 #address-cells = <2>;
635 #size-cells = <2>;
639 dma-names = "tx", "rx1", "rx2";
642 compatible = "inside-secure,safexcel-eip76";
645 status = "disabled"; /* Used by OP-TEE */
649 wkup_vtm0: temperature-sensor@42040000 {
650 compatible = "ti,j7200-vtm";
653 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
654 #thermal-sensor-cells = <1>;
658 compatible = "ti,j721e-esm";
660 ti,esm-pins = <95>;
661 bootph-pre-ram;
668 reg-names = "m_can", "message_ram";
669 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
671 clock-names = "hclk", "cclk";
674 interrupt-names = "int0", "int1";
675 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
683 reg-names = "m_can", "message_ram";
684 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
686 clock-names = "hclk", "cclk";
689 interrupt-names = "int0", "int1";
690 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;