Lines Matching +full:0 +full:x42050000
19 reg = <0x00 0x44083000 0x00 0x1000>;
40 reg = <0x00 0x40400000 0x00 0x400>;
53 reg = <0x00 0x40410000 0x00 0x400>;
57 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
66 reg = <0x00 0x40420000 0x00 0x400>;
79 reg = <0x00 0x40430000 0x00 0x400>;
83 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
92 reg = <0x00 0x40440000 0x00 0x400>;
105 reg = <0x00 0x40450000 0x00 0x400>;
109 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
118 reg = <0x00 0x40460000 0x00 0x400>;
131 reg = <0x00 0x40470000 0x00 0x400>;
135 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>;
144 reg = <0x00 0x40480000 0x00 0x400>;
157 reg = <0x00 0x40490000 0x00 0x400>;
161 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>;
171 ranges = <0x0 0x0 0x40f00000 0x20000>;
175 reg = <0x200 0x8>;
180 reg = <0x4040 0x4>;
189 ranges = <0x0 0x00 0x43000000 0x20000>;
193 reg = <0x14 0x4>;
200 reg = <0x0 0x40f04200 0x0 0x28>;
203 pinctrl-single,function-mask = <0x0000000F>;
210 reg = <0x0 0x40f04280 0x0 0x28>;
213 pinctrl-single,function-mask = <0x0000000F>;
219 /* Proxy 0 addressing */
220 reg = <0x00 0x4301c000 0x00 0x34>;
223 pinctrl-single,function-mask = <0xffffffff>;
228 /* Proxy 0 addressing */
229 reg = <0x00 0x4301c038 0x00 0x8>;
232 pinctrl-single,function-mask = <0xffffffff>;
237 /* Proxy 0 addressing */
238 reg = <0x00 0x4301c068 0x00 0xec>;
241 pinctrl-single,function-mask = <0xffffffff>;
246 /* Proxy 0 addressing */
247 reg = <0x00 0x4301c174 0x00 0x20>;
250 pinctrl-single,function-mask = <0xffffffff>;
255 reg = <0x00 0x41c00000 0x00 0x100000>;
256 ranges = <0x00 0x00 0x41c00000 0x100000>;
263 reg = <0x00 0x42300000 0x00 0x100>;
274 reg = <0x00 0x40a00000 0x00 0x100>;
285 reg = <0x00 0x42200000 0x00 0x400>;
297 reg = <0x00 0x42110000 0x00 0x100>;
305 ti,davinci-gpio-unbanked = <0>;
307 clocks = <&k3_clks 113 0>;
314 reg = <0x00 0x42100000 0x00 0x100>;
322 ti,davinci-gpio-unbanked = <0>;
324 clocks = <&k3_clks 114 0>;
333 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
340 reg = <0x00 0x2b800000 0x00 0x400000>,
341 <0x00 0x2b000000 0x00 0x400000>,
342 <0x00 0x28590000 0x00 0x100>,
343 <0x00 0x2a500000 0x00 0x40000>,
344 <0x00 0x28440000 0x00 0x40000>;
348 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
356 reg = <0x00 0x285c0000 0x00 0x100>,
357 <0x00 0x2a800000 0x00 0x40000>,
358 <0x00 0x2aa00000 0x00 0x40000>,
359 <0x00 0x284a0000 0x00 0x4000>,
360 <0x00 0x284c0000 0x00 0x4000>,
361 <0x00 0x28400000 0x00 0x2000>;
371 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
372 <0x0f>; /* TX_HCHAN */
373 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
374 <0x0b>; /* RX_HCHAN */
375 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
383 reg = <0x0 0x2a480000 0x0 0x80000>,
384 <0x0 0x2a380000 0x0 0x80000>,
385 <0x0 0x2a400000 0x0 0x80000>;
398 reg = <0x00 0x46000000 0x00 0x200000>;
400 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
406 dmas = <&mcu_udmap 0xf000>,
407 <&mcu_udmap 0xf001>,
408 <&mcu_udmap 0xf002>,
409 <&mcu_udmap 0xf003>,
410 <&mcu_udmap 0xf004>,
411 <&mcu_udmap 0xf005>,
412 <&mcu_udmap 0xf006>,
413 <&mcu_udmap 0xf007>,
414 <&mcu_udmap 0x7000>;
421 #size-cells = <0>;
427 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
434 reg = <0x00 0xf00 0x00 0x100>;
436 #size-cells = <0>;
444 reg = <0x00 0x3d000 0x00 0x400>;
456 reg = <0x00 0x40b00000 0x00 0x100>;
459 #size-cells = <0>;
468 reg = <0x00 0x40b10000 0x00 0x100>;
471 #size-cells = <0>;
480 reg = <0x00 0x42120000 0x00 0x100>;
483 #size-cells = <0>;
492 reg = <0x00 0x040300000 0x00 0x400>;
495 #size-cells = <0>;
497 clocks = <&k3_clks 274 0>;
503 reg = <0x00 0x040310000 0x00 0x400>;
506 #size-cells = <0>;
508 clocks = <&k3_clks 275 0>;
514 reg = <0x00 0x040320000 0x00 0x400>;
517 #size-cells = <0>;
519 clocks = <&k3_clks 276 0>;
527 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */
528 <0x0 0x47034000 0x0 0x47040000 0x0 0x100>, /* HBMC Control */
529 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */
530 <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>; /* HBMC/OSPI0 Memory */
534 reg = <0x00 0x47000004 0x00 0x4>;
536 mux-reg-masks = <0x0 0x2>; /* HBMC select */
541 reg = <0x00 0x47034000 0x00 0x100>,
542 <0x05 0x00000000 0x01 0x0000000>;
544 clocks = <&k3_clks 102 0>;
549 mux-controls = <&hbmc_mux 0>;
554 reg = <0x0 0x47040000 0x0 0x100>,
555 <0x5 0x00000000 0x1 0x0000000>;
559 cdns,trigger-address = <0x0>;
560 clocks = <&k3_clks 103 0>;
561 assigned-clocks = <&k3_clks 103 0>;
566 #size-cells = <0>;
573 reg = <0x00 0x40200000 0x00 0x1000>;
575 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
576 clocks = <&k3_clks 0 1>;
577 assigned-clocks = <&k3_clks 0 3>;
580 dmas = <&main_udmap 0x7400>,
581 <&main_udmap 0x7401>;
595 ranges = <0x41000000 0x00 0x41000000 0x20000>,
596 <0x41400000 0x00 0x41400000 0x20000>;
601 reg = <0x41000000 0x00010000>,
602 <0x41010000 0x00010000>;
606 ti,sci-proc-ids = <0x01 0xff>;
616 reg = <0x41400000 0x00008000>,
617 <0x41410000 0x00008000>;
621 ti,sci-proc-ids = <0x02 0xff>;
632 reg = <0x00 0x40900000 0x00 0x1200>;
636 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
637 dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
638 <&mcu_udmap 0x7503>;
643 reg = <0x00 0x40910000 0x00 0x7d>;
651 reg = <0x00 0x42040000 0x00 0x350>,
652 <0x00 0x42050000 0x00 0x350>;
659 reg = <0x00 0x40800000 0x00 0x1000>;
666 reg = <0x00 0x40528000 0x00 0x200>,
667 <0x00 0x40500000 0x00 0x8000>;
670 clocks = <&k3_clks 172 0>, <&k3_clks 172 2>;
675 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
681 reg = <0x00 0x40568000 0x00 0x200>,
682 <0x00 0x40540000 0x00 0x8000>;
685 clocks = <&k3_clks 173 0>, <&k3_clks 173 2>;
690 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;