Lines Matching +full:num +full:- +full:intr +full:- +full:inputs
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 pcie1_ctrl: pcie-ctrl@4074 {
36 compatible = "ti,j784s4-pcie-ctrl", "syscon";
40 serdes_ln_ctrl: mux-controller@4080 {
41 compatible = "reg-mux";
43 #mux-control-cells = <1>;
44 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
49 compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
50 ti,qsgmii-main-ports = <1>;
52 #phy-cells = <1>;
55 usb_serdes_mux: mux-controller@4000 {
56 compatible = "reg-mux";
58 #mux-control-cells = <1>;
59 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
63 gic500: interrupt-controller@1800000 {
64 compatible = "arm,gic-v3";
65 #address-cells = <2>;
66 #size-cells = <2>;
68 #interrupt-cells = <3>;
69 interrupt-controller;
79 gic_its: msi-controller@1820000 {
80 compatible = "arm,gic-v3-its";
82 socionext,synquacer-pre-its = <0x1000000 0x400000>;
83 msi-controller;
84 #msi-cells = <1>;
88 main_gpio_intr: interrupt-controller@a00000 {
89 compatible = "ti,sci-intr";
91 ti,intr-trigger-type = <1>;
92 interrupt-controller;
93 interrupt-parent = <&gic500>;
94 #interrupt-cells = <1>;
96 ti,sci-dev-id = <131>;
97 ti,interrupt-ranges = <8 392 56>;
101 compatible = "simple-bus";
102 #address-cells = <2>;
103 #size-cells = <2>;
105 ti,sci-dev-id = <199>;
106 dma-coherent;
107 dma-ranges;
109 main_navss_intr: interrupt-controller@310e0000 {
110 compatible = "ti,sci-intr";
112 ti,intr-trigger-type = <4>;
113 interrupt-controller;
114 interrupt-parent = <&gic500>;
115 #interrupt-cells = <1>;
117 ti,sci-dev-id = <213>;
118 ti,interrupt-ranges = <0 64 64>,
123 main_udmass_inta: msi-controller@33d00000 {
124 compatible = "ti,sci-inta";
126 interrupt-controller;
127 #interrupt-cells = <0>;
128 interrupt-parent = <&main_navss_intr>;
129 msi-controller;
131 ti,sci-dev-id = <209>;
132 ti,interrupt-ranges = <0 0 256>;
136 compatible = "ti,am654-secure-proxy";
137 #mbox-cells = <1>;
138 reg-names = "target_data", "rt", "scfg";
142 interrupt-names = "rx_011";
144 bootph-all;
148 compatible = "ti,am654-hwspinlock";
150 #hwlock-cells = <1>;
154 compatible = "ti,am654-mailbox";
156 #mbox-cells = <1>;
157 ti,mbox-num-users = <4>;
158 ti,mbox-num-fifos = <16>;
159 interrupt-parent = <&main_navss_intr>;
164 compatible = "ti,am654-mailbox";
166 #mbox-cells = <1>;
167 ti,mbox-num-users = <4>;
168 ti,mbox-num-fifos = <16>;
169 interrupt-parent = <&main_navss_intr>;
174 compatible = "ti,am654-mailbox";
176 #mbox-cells = <1>;
177 ti,mbox-num-users = <4>;
178 ti,mbox-num-fifos = <16>;
179 interrupt-parent = <&main_navss_intr>;
184 compatible = "ti,am654-mailbox";
186 #mbox-cells = <1>;
187 ti,mbox-num-users = <4>;
188 ti,mbox-num-fifos = <16>;
189 interrupt-parent = <&main_navss_intr>;
194 compatible = "ti,am654-mailbox";
196 #mbox-cells = <1>;
197 ti,mbox-num-users = <4>;
198 ti,mbox-num-fifos = <16>;
199 interrupt-parent = <&main_navss_intr>;
204 compatible = "ti,am654-mailbox";
206 #mbox-cells = <1>;
207 ti,mbox-num-users = <4>;
208 ti,mbox-num-fifos = <16>;
209 interrupt-parent = <&main_navss_intr>;
214 compatible = "ti,am654-mailbox";
216 #mbox-cells = <1>;
217 ti,mbox-num-users = <4>;
218 ti,mbox-num-fifos = <16>;
219 interrupt-parent = <&main_navss_intr>;
224 compatible = "ti,am654-mailbox";
226 #mbox-cells = <1>;
227 ti,mbox-num-users = <4>;
228 ti,mbox-num-fifos = <16>;
229 interrupt-parent = <&main_navss_intr>;
234 compatible = "ti,am654-mailbox";
236 #mbox-cells = <1>;
237 ti,mbox-num-users = <4>;
238 ti,mbox-num-fifos = <16>;
239 interrupt-parent = <&main_navss_intr>;
244 compatible = "ti,am654-mailbox";
246 #mbox-cells = <1>;
247 ti,mbox-num-users = <4>;
248 ti,mbox-num-fifos = <16>;
249 interrupt-parent = <&main_navss_intr>;
254 compatible = "ti,am654-mailbox";
256 #mbox-cells = <1>;
257 ti,mbox-num-users = <4>;
258 ti,mbox-num-fifos = <16>;
259 interrupt-parent = <&main_navss_intr>;
264 compatible = "ti,am654-mailbox";
266 #mbox-cells = <1>;
267 ti,mbox-num-users = <4>;
268 ti,mbox-num-fifos = <16>;
269 interrupt-parent = <&main_navss_intr>;
274 compatible = "ti,am654-navss-ringacc";
280 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
281 ti,num-rings = <1024>;
282 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
284 ti,sci-dev-id = <211>;
285 msi-parent = <&main_udmass_inta>;
288 main_udmap: dma-controller@31150000 {
289 compatible = "ti,j721e-navss-main-udmap";
296 reg-names = "gcfg", "rchanrt", "tchanrt",
298 msi-parent = <&main_udmass_inta>;
299 #dma-cells = <1>;
302 ti,sci-dev-id = <212>;
305 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
308 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
311 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
315 compatible = "ti,j721e-cpts";
317 reg-names = "cpts";
319 clock-names = "cpts";
320 interrupts-extended = <&main_navss_intr 391>;
321 interrupt-names = "cpts";
322 ti,cpts-periodic-outputs = <6>;
323 ti,cpts-ext-ts-inputs = <8>;
328 compatible = "ti,j7200-cpswxg-nuss";
329 #address-cells = <2>;
330 #size-cells = <2>;
332 reg-names = "cpsw_nuss";
335 clock-names = "fck";
336 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
347 dma-names = "tx0", "tx1", "tx2", "tx3",
353 ethernet-ports {
354 #address-cells = <1>;
355 #size-cells = <0>;
358 ti,mac-only;
365 ti,mac-only;
372 ti,mac-only;
379 ti,mac-only;
386 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
388 #address-cells = <1>;
389 #size-cells = <0>;
391 clock-names = "fck";
397 compatible = "ti,j721e-cpts";
400 clock-names = "cpts";
401 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "cpts";
403 ti,cpts-ext-ts-inputs = <4>;
404 ti,cpts-periodic-outputs = <2>;
410 compatible = "ti,j7200-padconf", "pinctrl-single";
412 #pinctrl-cells = <1>;
413 pinctrl-single,register-width = <32>;
414 pinctrl-single,function-mask = <0x000001ff>;
419 compatible = "ti,j7200-padconf", "pinctrl-single";
421 #pinctrl-cells = <1>;
422 pinctrl-single,register-width = <32>;
423 pinctrl-single,function-mask = <0x0000001f>;
427 compatible = "ti,j7200-padconf", "pinctrl-single";
430 #pinctrl-cells = <1>;
431 pinctrl-single,register-width = <32>;
432 pinctrl-single,function-mask = <0xffffffff>;
436 compatible = "ti,j7200-padconf", "pinctrl-single";
439 #pinctrl-cells = <1>;
440 pinctrl-single,register-width = <32>;
441 pinctrl-single,function-mask = <0xffffffff>;
445 compatible = "ti,j7200-padconf", "pinctrl-single";
448 #pinctrl-cells = <1>;
449 pinctrl-single,register-width = <32>;
450 pinctrl-single,function-mask = <0xffffffff>;
454 compatible = "ti,j7200-padconf", "pinctrl-single";
457 #pinctrl-cells = <1>;
458 pinctrl-single,register-width = <32>;
459 pinctrl-single,function-mask = <0xffffffff>;
463 compatible = "ti,j721e-uart", "ti,am654-uart";
466 clock-frequency = <48000000>;
467 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
469 clock-names = "fclk";
474 compatible = "ti,j721e-uart", "ti,am654-uart";
477 clock-frequency = <48000000>;
478 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
480 clock-names = "fclk";
485 compatible = "ti,j721e-uart", "ti,am654-uart";
488 clock-frequency = <48000000>;
489 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
491 clock-names = "fclk";
496 compatible = "ti,j721e-uart", "ti,am654-uart";
499 clock-frequency = <48000000>;
500 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
502 clock-names = "fclk";
507 compatible = "ti,j721e-uart", "ti,am654-uart";
510 clock-frequency = <48000000>;
511 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
513 clock-names = "fclk";
518 compatible = "ti,j721e-uart", "ti,am654-uart";
521 clock-frequency = <48000000>;
522 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
524 clock-names = "fclk";
529 compatible = "ti,j721e-uart", "ti,am654-uart";
532 clock-frequency = <48000000>;
533 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
535 clock-names = "fclk";
540 compatible = "ti,j721e-uart", "ti,am654-uart";
543 clock-frequency = <48000000>;
544 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
546 clock-names = "fclk";
551 compatible = "ti,j721e-uart", "ti,am654-uart";
554 clock-frequency = <48000000>;
555 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
557 clock-names = "fclk";
562 compatible = "ti,j721e-uart", "ti,am654-uart";
565 clock-frequency = <48000000>;
566 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
568 clock-names = "fclk";
573 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
576 #address-cells = <1>;
577 #size-cells = <0>;
578 clock-names = "fck";
580 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
585 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
588 #address-cells = <1>;
589 #size-cells = <0>;
590 clock-names = "fck";
592 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
597 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
600 #address-cells = <1>;
601 #size-cells = <0>;
602 clock-names = "fck";
604 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
609 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
612 #address-cells = <1>;
613 #size-cells = <0>;
614 clock-names = "fck";
616 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
621 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
624 #address-cells = <1>;
625 #size-cells = <0>;
626 clock-names = "fck";
628 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
633 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
636 #address-cells = <1>;
637 #size-cells = <0>;
638 clock-names = "fck";
640 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
645 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
648 #address-cells = <1>;
649 #size-cells = <0>;
650 clock-names = "fck";
652 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
657 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
660 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
661 clock-names = "clk_ahb", "clk_xin";
663 ti,otap-del-sel-legacy = <0x0>;
664 ti,otap-del-sel-mmc-hs = <0x0>;
665 ti,otap-del-sel-ddr52 = <0x6>;
666 ti,otap-del-sel-hs200 = <0x8>;
667 ti,otap-del-sel-hs400 = <0x5>;
668 ti,itap-del-sel-legacy = <0x10>;
669 ti,itap-del-sel-mmc-hs = <0xa>;
670 ti,itap-del-sel-ddr52 = <0x3>;
671 ti,strobe-sel = <0x77>;
672 ti,clkbuf-sel = <0x7>;
673 ti,trm-icp = <0x8>;
674 bus-width = <8>;
675 mmc-ddr-1_8v;
676 mmc-hs200-1_8v;
677 mmc-hs400-1_8v;
678 dma-coherent;
683 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
686 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
687 clock-names = "clk_ahb", "clk_xin";
689 ti,otap-del-sel-legacy = <0x0>;
690 ti,otap-del-sel-sd-hs = <0x0>;
691 ti,otap-del-sel-sdr12 = <0xf>;
692 ti,otap-del-sel-sdr25 = <0xf>;
693 ti,otap-del-sel-sdr50 = <0xc>;
694 ti,otap-del-sel-sdr104 = <0x5>;
695 ti,otap-del-sel-ddr50 = <0xc>;
696 ti,itap-del-sel-legacy = <0x0>;
697 ti,itap-del-sel-sd-hs = <0x0>;
698 ti,itap-del-sel-sdr12 = <0x0>;
699 ti,itap-del-sel-sdr25 = <0x0>;
700 ti,clkbuf-sel = <0x7>;
701 ti,trm-icp = <0x8>;
702 dma-coherent;
707 compatible = "ti,j721e-wiz-10g";
708 #address-cells = <1>;
709 #size-cells = <1>;
710 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
712 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
713 num-lanes = <4>;
714 #reset-cells = <1>;
717 assigned-clocks = <&k3_clks 292 85>;
718 assigned-clock-parents = <&k3_clks 292 89>;
720 wiz0_pll0_refclk: pll0-refclk {
722 clock-output-names = "wiz0_pll0_refclk";
723 #clock-cells = <0>;
724 assigned-clocks = <&wiz0_pll0_refclk>;
725 assigned-clock-parents = <&k3_clks 292 85>;
728 wiz0_pll1_refclk: pll1-refclk {
730 clock-output-names = "wiz0_pll1_refclk";
731 #clock-cells = <0>;
732 assigned-clocks = <&wiz0_pll1_refclk>;
733 assigned-clock-parents = <&k3_clks 292 85>;
736 wiz0_refclk_dig: refclk-dig {
738 clock-output-names = "wiz0_refclk_dig";
739 #clock-cells = <0>;
740 assigned-clocks = <&wiz0_refclk_dig>;
741 assigned-clock-parents = <&k3_clks 292 85>;
744 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
746 #clock-cells = <0>;
750 compatible = "ti,j721e-serdes-10g";
752 reg-names = "torrent_phy";
754 reset-names = "torrent_reset";
756 clock-names = "refclk";
757 #address-cells = <1>;
758 #size-cells = <0>;
763 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
768 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
769 interrupt-names = "link_state";
772 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
773 max-link-speed = <3>;
774 num-lanes = <4>;
775 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
777 clock-names = "fck";
778 #address-cells = <3>;
779 #size-cells = <2>;
780 bus-range = <0x0 0xff>;
781 cdns,no-bar-match-nbits = <64>;
782 vendor-id = <0x104c>;
783 device-id = <0xb00f>;
784 msi-map = <0x0 &gic_its 0x0 0x10000>;
785 dma-coherent;
787 … 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4…
788 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
792 usbss0: cdns-usb@4104000 {
793 compatible = "ti,j721e-usb";
795 dma-coherent;
796 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
798 clock-names = "ref", "lpm";
799 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
800 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
801 #address-cells = <2>;
802 #size-cells = <2>;
810 reg-names = "otg", "xhci", "dev";
814 interrupt-names = "host",
817 maximum-speed = "super-speed";
819 cdns,phyrst-a-enable;
824 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
826 gpio-controller;
827 #gpio-cells = <2>;
828 interrupt-parent = <&main_gpio_intr>;
831 interrupt-controller;
832 #interrupt-cells = <2>;
834 ti,davinci-gpio-unbanked = <0>;
835 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
837 clock-names = "gpio";
842 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
844 gpio-controller;
845 #gpio-cells = <2>;
846 interrupt-parent = <&main_gpio_intr>;
849 interrupt-controller;
850 #interrupt-cells = <2>;
852 ti,davinci-gpio-unbanked = <0>;
853 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
855 clock-names = "gpio";
860 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
862 gpio-controller;
863 #gpio-cells = <2>;
864 interrupt-parent = <&main_gpio_intr>;
867 interrupt-controller;
868 #interrupt-cells = <2>;
870 ti,davinci-gpio-unbanked = <0>;
871 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
873 clock-names = "gpio";
878 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
880 gpio-controller;
881 #gpio-cells = <2>;
882 interrupt-parent = <&main_gpio_intr>;
885 interrupt-controller;
886 #interrupt-cells = <2>;
888 ti,davinci-gpio-unbanked = <0>;
889 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
891 clock-names = "gpio";
899 reg-names = "m_can", "message_ram";
900 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
902 clock-names = "hclk", "cclk";
905 interrupt-names = "int0", "int1";
906 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
914 reg-names = "m_can", "message_ram";
915 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
917 clock-names = "hclk", "cclk";
920 interrupt-names = "int0", "int1";
921 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
929 reg-names = "m_can", "message_ram";
930 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
932 clock-names = "hclk", "cclk";
935 interrupt-names = "int0", "int1";
936 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
944 reg-names = "m_can", "message_ram";
945 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
947 clock-names = "hclk", "cclk";
950 interrupt-names = "int0", "int1";
951 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
959 reg-names = "m_can", "message_ram";
960 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
962 clock-names = "hclk", "cclk";
965 interrupt-names = "int0", "int1";
966 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
974 reg-names = "m_can", "message_ram";
975 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
977 clock-names = "hclk", "cclk";
980 interrupt-names = "int0", "int1";
981 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
989 reg-names = "m_can", "message_ram";
990 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
992 clock-names = "hclk", "cclk";
995 interrupt-names = "int0", "int1";
996 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1004 reg-names = "m_can", "message_ram";
1005 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
1007 clock-names = "hclk", "cclk";
1010 interrupt-names = "int0", "int1";
1011 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1019 reg-names = "m_can", "message_ram";
1020 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
1022 clock-names = "hclk", "cclk";
1025 interrupt-names = "int0", "int1";
1026 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1034 reg-names = "m_can", "message_ram";
1035 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
1037 clock-names = "hclk", "cclk";
1040 interrupt-names = "int0", "int1";
1041 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1049 reg-names = "m_can", "message_ram";
1050 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
1052 clock-names = "hclk", "cclk";
1055 interrupt-names = "int0", "int1";
1056 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1064 reg-names = "m_can", "message_ram";
1065 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
1067 clock-names = "hclk", "cclk";
1070 interrupt-names = "int0", "int1";
1071 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1079 reg-names = "m_can", "message_ram";
1080 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
1082 clock-names = "hclk", "cclk";
1085 interrupt-names = "int0", "int1";
1086 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1094 reg-names = "m_can", "message_ram";
1095 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
1097 clock-names = "hclk", "cclk";
1100 interrupt-names = "int0", "int1";
1101 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1109 reg-names = "m_can", "message_ram";
1110 power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
1112 clock-names = "hclk", "cclk";
1115 interrupt-names = "int0", "int1";
1116 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1124 reg-names = "m_can", "message_ram";
1125 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1127 clock-names = "hclk", "cclk";
1130 interrupt-names = "int0", "int1";
1131 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1139 reg-names = "m_can", "message_ram";
1140 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1142 clock-names = "hclk", "cclk";
1145 interrupt-names = "int0", "int1";
1146 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1154 reg-names = "m_can", "message_ram";
1155 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
1157 clock-names = "hclk", "cclk";
1160 interrupt-names = "int0", "int1";
1161 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1166 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1171 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
1177 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1180 #address-cells = <1>;
1181 #size-cells = <0>;
1182 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
1188 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1191 #address-cells = <1>;
1192 #size-cells = <0>;
1193 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
1199 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1202 #address-cells = <1>;
1203 #size-cells = <0>;
1204 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
1210 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1213 #address-cells = <1>;
1214 #size-cells = <0>;
1215 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
1221 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1226 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
1232 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1235 #address-cells = <1>;
1236 #size-cells = <0>;
1237 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
1243 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1248 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
1254 compatible = "ti,j7-rti-wdt";
1257 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1258 assigned-clocks = <&k3_clks 252 1>;
1259 assigned-clock-parents = <&k3_clks 252 5>;
1263 compatible = "ti,j7-rti-wdt";
1266 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1267 assigned-clocks = <&k3_clks 253 1>;
1268 assigned-clock-parents = <&k3_clks 253 5>;
1272 compatible = "ti,am654-timer";
1276 clock-names = "fck";
1277 assigned-clocks = <&k3_clks 49 1>;
1278 assigned-clock-parents = <&k3_clks 49 2>;
1279 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1280 ti,timer-pwm;
1284 compatible = "ti,am654-timer";
1288 clock-names = "fck";
1289 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1290 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
1291 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1292 ti,timer-pwm;
1296 compatible = "ti,am654-timer";
1300 clock-names = "fck";
1301 assigned-clocks = <&k3_clks 51 1>;
1302 assigned-clock-parents = <&k3_clks 51 2>;
1303 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1304 ti,timer-pwm;
1308 compatible = "ti,am654-timer";
1312 clock-names = "fck";
1313 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1314 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
1315 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1316 ti,timer-pwm;
1320 compatible = "ti,am654-timer";
1324 clock-names = "fck";
1325 assigned-clocks = <&k3_clks 53 1>;
1326 assigned-clock-parents = <&k3_clks 53 2>;
1327 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1328 ti,timer-pwm;
1332 compatible = "ti,am654-timer";
1336 clock-names = "fck";
1337 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1338 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
1339 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1340 ti,timer-pwm;
1344 compatible = "ti,am654-timer";
1348 clock-names = "fck";
1349 assigned-clocks = <&k3_clks 55 1>;
1350 assigned-clock-parents = <&k3_clks 55 2>;
1351 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1352 ti,timer-pwm;
1356 compatible = "ti,am654-timer";
1360 clock-names = "fck";
1361 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1362 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
1363 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1364 ti,timer-pwm;
1368 compatible = "ti,am654-timer";
1372 clock-names = "fck";
1373 assigned-clocks = <&k3_clks 58 1>;
1374 assigned-clock-parents = <&k3_clks 58 2>;
1375 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1376 ti,timer-pwm;
1380 compatible = "ti,am654-timer";
1384 clock-names = "fck";
1385 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1386 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
1387 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1388 ti,timer-pwm;
1392 compatible = "ti,am654-timer";
1396 clock-names = "fck";
1397 assigned-clocks = <&k3_clks 60 1>;
1398 assigned-clock-parents = <&k3_clks 60 2>;
1399 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1400 ti,timer-pwm;
1404 compatible = "ti,am654-timer";
1408 clock-names = "fck";
1409 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1410 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
1411 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1412 ti,timer-pwm;
1416 compatible = "ti,am654-timer";
1420 clock-names = "fck";
1421 assigned-clocks = <&k3_clks 63 1>;
1422 assigned-clock-parents = <&k3_clks 63 2>;
1423 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1424 ti,timer-pwm;
1428 compatible = "ti,am654-timer";
1432 clock-names = "fck";
1433 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1434 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
1435 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1436 ti,timer-pwm;
1440 compatible = "ti,am654-timer";
1444 clock-names = "fck";
1445 assigned-clocks = <&k3_clks 65 1>;
1446 assigned-clock-parents = <&k3_clks 65 2>;
1447 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1448 ti,timer-pwm;
1452 compatible = "ti,am654-timer";
1456 clock-names = "fck";
1457 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1458 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
1459 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1460 ti,timer-pwm;
1464 compatible = "ti,am654-timer";
1468 clock-names = "fck";
1469 assigned-clocks = <&k3_clks 67 1>;
1470 assigned-clock-parents = <&k3_clks 67 2>;
1471 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1472 ti,timer-pwm;
1476 compatible = "ti,am654-timer";
1480 clock-names = "fck";
1481 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1482 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
1483 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1484 ti,timer-pwm;
1488 compatible = "ti,am654-timer";
1492 clock-names = "fck";
1493 assigned-clocks = <&k3_clks 69 1>;
1494 assigned-clock-parents = <&k3_clks 69 2>;
1495 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1496 ti,timer-pwm;
1500 compatible = "ti,am654-timer";
1504 clock-names = "fck";
1505 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1506 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
1507 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1508 ti,timer-pwm;
1512 compatible = "ti,j7200-r5fss";
1513 ti,cluster-mode = <1>;
1514 #address-cells = <1>;
1515 #size-cells = <1>;
1518 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1521 compatible = "ti,j7200-r5f";
1524 reg-names = "atcm", "btcm";
1526 ti,sci-dev-id = <245>;
1527 ti,sci-proc-ids = <0x06 0xff>;
1529 firmware-name = "j7200-main-r5f0_0-fw";
1530 ti,atcm-enable = <1>;
1531 ti,btcm-enable = <1>;
1536 compatible = "ti,j7200-r5f";
1539 reg-names = "atcm", "btcm";
1541 ti,sci-dev-id = <246>;
1542 ti,sci-proc-ids = <0x07 0xff>;
1544 firmware-name = "j7200-main-r5f0_1-fw";
1545 ti,atcm-enable = <1>;
1546 ti,btcm-enable = <1>;
1552 compatible = "ti,j721e-esm";
1554 bootph-pre-ram;
1555 ti,esm-pins = <656>, <657>;