Lines Matching +full:0 +full:x33d00000
10 #clock-cells = <0>;
18 reg = <0x00 0x70000000 0x00 0x100000>;
21 ranges = <0x00 0x00 0x70000000 0x100000>;
23 atf-sram@0 {
24 reg = <0x00 0x20000>;
30 reg = <0x00 0x00100000 0x00 0x1c000>;
33 ranges = <0x00 0x00 0x00100000 0x1c000>;
37 reg = <0x4080 0x20>;
39 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
40 <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
46 reg = <0x4044 0x10>;
52 reg = <0x4000 0x4>;
54 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
65 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
66 <0x00 0x01900000 0x00 0x100000>, /* GICR */
67 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
68 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
69 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
76 reg = <0x00 0x01820000 0x00 0x10000>;
77 socionext,synquacer-pre-its = <0x1000000 0x400000>;
85 reg = <0x00 0x00a00000 0x00 0x800>;
99 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
106 reg = <0x00 0x310e0000 0x00 0x4000>;
113 ti,interrupt-ranges = <0 64 64>,
120 reg = <0x00 0x33d00000 0x00 0x100000>;
122 #interrupt-cells = <0>;
127 ti,interrupt-ranges = <0 0 256>;
134 reg = <0x00 0x32c00000 0x00 0x100000>,
135 <0x00 0x32400000 0x00 0x100000>,
136 <0x00 0x32800000 0x00 0x100000>;
143 reg = <0x00 0x30e00000 0x00 0x1000>;
149 reg = <0x00 0x31f80000 0x00 0x200>;
159 reg = <0x00 0x31f81000 0x00 0x200>;
169 reg = <0x00 0x31f82000 0x00 0x200>;
179 reg = <0x00 0x31f83000 0x00 0x200>;
189 reg = <0x00 0x31f84000 0x00 0x200>;
199 reg = <0x00 0x31f85000 0x00 0x200>;
209 reg = <0x00 0x31f86000 0x00 0x200>;
219 reg = <0x00 0x31f87000 0x00 0x200>;
229 reg = <0x00 0x31f88000 0x00 0x200>;
239 reg = <0x00 0x31f89000 0x00 0x200>;
249 reg = <0x00 0x31f8a000 0x00 0x200>;
259 reg = <0x00 0x31f8b000 0x00 0x200>;
269 reg = <0x00 0x3c000000 0x00 0x400000>,
270 <0x00 0x38000000 0x00 0x400000>,
271 <0x00 0x31120000 0x00 0x100>,
272 <0x00 0x33000000 0x00 0x40000>,
273 <0x00 0x31080000 0x00 0x40000>;
276 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
284 reg = <0x00 0x31150000 0x00 0x100>,
285 <0x00 0x34000000 0x00 0x100000>,
286 <0x00 0x35000000 0x00 0x100000>,
287 <0x00 0x30b00000 0x00 0x4000>,
288 <0x00 0x30c00000 0x00 0x4000>,
289 <0x00 0x30d00000 0x00 0x4000>;
299 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
300 <0x0f>, /* TX_HCHAN */
301 <0x10>; /* TX_UHCHAN */
302 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
303 <0x0b>, /* RX_HCHAN */
304 <0x0c>; /* RX_UHCHAN */
305 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
310 reg = <0x00 0x310d0000 0x00 0x400>;
325 reg = <0x00 0xc000000 0x00 0x200000>;
327 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
332 dmas = <&main_udmap 0xca00>,
333 <&main_udmap 0xca01>,
334 <&main_udmap 0xca02>,
335 <&main_udmap 0xca03>,
336 <&main_udmap 0xca04>,
337 <&main_udmap 0xca05>,
338 <&main_udmap 0xca06>,
339 <&main_udmap 0xca07>,
340 <&main_udmap 0x4a00>;
349 #size-cells = <0>;
381 reg = <0x00 0xf00 0x00 0x100>;
383 #size-cells = <0>;
392 reg = <0x00 0x3d000 0x00 0x400>;
405 reg = <0x0 0x104200 0x0 0x50>;
408 pinctrl-single,function-mask = <0x000001ff>;
414 reg = <0x0 0x104280 0x0 0x20>;
417 pinctrl-single,function-mask = <0x0000001f>;
422 /* Proxy 0 addressing */
423 reg = <0x00 0x11c000 0x00 0x10c>;
426 pinctrl-single,function-mask = <0xffffffff>;
431 /* Proxy 0 addressing */
432 reg = <0x00 0x11c11c 0x00 0xc>;
435 pinctrl-single,function-mask = <0xffffffff>;
440 reg = <0x00 0x02800000 0x00 0x100>;
451 reg = <0x00 0x02810000 0x00 0x100>;
462 reg = <0x00 0x02820000 0x00 0x100>;
473 reg = <0x00 0x02830000 0x00 0x100>;
484 reg = <0x00 0x02840000 0x00 0x100>;
495 reg = <0x00 0x02850000 0x00 0x100>;
506 reg = <0x00 0x02860000 0x00 0x100>;
517 reg = <0x00 0x02870000 0x00 0x100>;
528 reg = <0x00 0x02880000 0x00 0x100>;
539 reg = <0x00 0x02890000 0x00 0x100>;
550 reg = <0x00 0x2000000 0x00 0x100>;
553 #size-cells = <0>;
562 reg = <0x00 0x2010000 0x00 0x100>;
565 #size-cells = <0>;
574 reg = <0x00 0x2020000 0x00 0x100>;
577 #size-cells = <0>;
586 reg = <0x00 0x2030000 0x00 0x100>;
589 #size-cells = <0>;
598 reg = <0x00 0x2040000 0x00 0x100>;
601 #size-cells = <0>;
610 reg = <0x00 0x2050000 0x00 0x100>;
613 #size-cells = <0>;
622 reg = <0x00 0x2060000 0x00 0x100>;
625 #size-cells = <0>;
634 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
638 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
639 ti,otap-del-sel-legacy = <0x0>;
640 ti,otap-del-sel-mmc-hs = <0x0>;
641 ti,otap-del-sel-ddr52 = <0x6>;
642 ti,otap-del-sel-hs200 = <0x8>;
643 ti,otap-del-sel-hs400 = <0x5>;
644 ti,itap-del-sel-legacy = <0x10>;
645 ti,itap-del-sel-mmc-hs = <0xa>;
646 ti,itap-del-sel-ddr52 = <0x3>;
647 ti,strobe-sel = <0x77>;
648 ti,clkbuf-sel = <0x7>;
649 ti,trm-icp = <0x8>;
660 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
665 ti,otap-del-sel-legacy = <0x0>;
666 ti,otap-del-sel-sd-hs = <0x0>;
667 ti,otap-del-sel-sdr12 = <0xf>;
668 ti,otap-del-sel-sdr25 = <0xf>;
669 ti,otap-del-sel-sdr50 = <0xc>;
670 ti,otap-del-sel-sdr104 = <0x5>;
671 ti,otap-del-sel-ddr50 = <0xc>;
672 ti,itap-del-sel-legacy = <0x0>;
673 ti,itap-del-sel-sd-hs = <0x0>;
674 ti,itap-del-sel-sdr12 = <0x0>;
675 ti,itap-del-sel-sdr25 = <0x0>;
676 ti,clkbuf-sel = <0x7>;
677 ti,trm-icp = <0x8>;
691 ranges = <0x5060000 0x0 0x5060000 0x10000>;
699 #clock-cells = <0>;
707 #clock-cells = <0>;
715 #clock-cells = <0>;
722 #clock-cells = <0>;
727 reg = <0x05060000 0x00010000>;
729 resets = <&serdes_wiz0 0>;
734 #size-cells = <0>;
740 reg = <0x00 0x02910000 0x00 0x1000>,
741 <0x00 0x02917000 0x00 0x400>,
742 <0x00 0x0d800000 0x00 0x00800000>,
743 <0x00 0x18000000 0x00 0x00001000>;
748 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
756 bus-range = <0x0 0xff>;
758 vendor-id = <0x104c>;
759 device-id = <0xb00f>;
760 msi-map = <0x0 &gic_its 0x0 0x10000>;
762 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
763 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
764 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
770 reg = <0x00 0x4104000 0x00 0x100>;
783 reg = <0x00 0x6000000 0x00 0x10000>,
784 <0x00 0x6010000 0x00 0x10000>,
785 <0x00 0x6020000 0x00 0x10000>;
787 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
789 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
801 reg = <0x00 0x00600000 0x00 0x100>;
810 ti,davinci-gpio-unbanked = <0>;
812 clocks = <&k3_clks 105 0>;
819 reg = <0x00 0x00610000 0x00 0x100>;
828 ti,davinci-gpio-unbanked = <0>;
830 clocks = <&k3_clks 107 0>;
837 reg = <0x00 0x00620000 0x00 0x100>;
846 ti,davinci-gpio-unbanked = <0>;
848 clocks = <&k3_clks 109 0>;
855 reg = <0x00 0x00630000 0x00 0x100>;
864 ti,davinci-gpio-unbanked = <0>;
866 clocks = <&k3_clks 111 0>;
873 reg = <0x00 0x02701000 0x00 0x200>,
874 <0x00 0x02708000 0x00 0x8000>;
877 clocks = <&k3_clks 156 0>, <&k3_clks 156 2>;
882 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
888 reg = <0x00 0x02711000 0x00 0x200>,
889 <0x00 0x02718000 0x00 0x8000>;
892 clocks = <&k3_clks 158 0>, <&k3_clks 158 2>;
897 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
903 reg = <0x00 0x02721000 0x00 0x200>,
904 <0x00 0x02728000 0x00 0x8000>;
907 clocks = <&k3_clks 160 0>, <&k3_clks 160 2>;
912 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
918 reg = <0x00 0x02731000 0x00 0x200>,
919 <0x00 0x02738000 0x00 0x8000>;
922 clocks = <&k3_clks 161 0>, <&k3_clks 161 2>;
927 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
933 reg = <0x00 0x02741000 0x00 0x200>,
934 <0x00 0x02748000 0x00 0x8000>;
937 clocks = <&k3_clks 162 0>, <&k3_clks 162 2>;
942 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
948 reg = <0x00 0x02751000 0x00 0x200>,
949 <0x00 0x02758000 0x00 0x8000>;
952 clocks = <&k3_clks 163 0>, <&k3_clks 163 2>;
957 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
963 reg = <0x00 0x02761000 0x00 0x200>,
964 <0x00 0x02768000 0x00 0x8000>;
967 clocks = <&k3_clks 164 0>, <&k3_clks 164 2>;
972 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
978 reg = <0x00 0x02771000 0x00 0x200>,
979 <0x00 0x02778000 0x00 0x8000>;
982 clocks = <&k3_clks 165 0>, <&k3_clks 165 2>;
987 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
993 reg = <0x00 0x02781000 0x00 0x200>,
994 <0x00 0x02788000 0x00 0x8000>;
997 clocks = <&k3_clks 166 0>, <&k3_clks 166 2>;
1002 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1008 reg = <0x00 0x02791000 0x00 0x200>,
1009 <0x00 0x02798000 0x00 0x8000>;
1012 clocks = <&k3_clks 167 0>, <&k3_clks 167 2>;
1017 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1023 reg = <0x00 0x027a1000 0x00 0x200>,
1024 <0x00 0x027a8000 0x00 0x8000>;
1027 clocks = <&k3_clks 168 0>, <&k3_clks 168 2>;
1032 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1038 reg = <0x00 0x027b1000 0x00 0x200>,
1039 <0x00 0x027b8000 0x00 0x8000>;
1042 clocks = <&k3_clks 169 0>, <&k3_clks 169 2>;
1047 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1053 reg = <0x00 0x027c1000 0x00 0x200>,
1054 <0x00 0x027c8000 0x00 0x8000>;
1057 clocks = <&k3_clks 170 0>, <&k3_clks 170 2>;
1062 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1068 reg = <0x00 0x027d1000 0x00 0x200>,
1069 <0x00 0x027d8000 0x00 0x8000>;
1072 clocks = <&k3_clks 171 0>, <&k3_clks 171 2>;
1077 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1083 reg = <0x00 0x02681000 0x00 0x200>,
1084 <0x00 0x02688000 0x00 0x8000>;
1087 clocks = <&k3_clks 150 0>, <&k3_clks 150 2>;
1092 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1098 reg = <0x00 0x02691000 0x00 0x200>,
1099 <0x00 0x02698000 0x00 0x8000>;
1102 clocks = <&k3_clks 151 0>, <&k3_clks 151 2>;
1107 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1113 reg = <0x00 0x026a1000 0x00 0x200>,
1114 <0x00 0x026a8000 0x00 0x8000>;
1117 clocks = <&k3_clks 152 0>, <&k3_clks 152 2>;
1122 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1128 reg = <0x00 0x026b1000 0x00 0x200>,
1129 <0x00 0x026b8000 0x00 0x8000>;
1132 clocks = <&k3_clks 153 0>, <&k3_clks 153 2>;
1137 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1143 reg = <0x00 0x02100000 0x00 0x400>;
1146 #size-cells = <0>;
1154 reg = <0x00 0x02110000 0x00 0x400>;
1157 #size-cells = <0>;
1165 reg = <0x00 0x02120000 0x00 0x400>;
1168 #size-cells = <0>;
1176 reg = <0x00 0x02130000 0x00 0x400>;
1179 #size-cells = <0>;
1187 reg = <0x00 0x02140000 0x00 0x400>;
1190 #size-cells = <0>;
1198 reg = <0x00 0x02150000 0x00 0x400>;
1201 #size-cells = <0>;
1209 reg = <0x00 0x02160000 0x00 0x400>;
1212 #size-cells = <0>;
1220 reg = <0x00 0x02170000 0x00 0x400>;
1223 #size-cells = <0>;
1231 reg = <0x0 0x2200000 0x0 0x100>;
1240 reg = <0x0 0x2210000 0x0 0x100>;
1249 reg = <0x00 0x2400000 0x00 0x400>;
1261 reg = <0x00 0x2410000 0x00 0x400>;
1265 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1273 reg = <0x00 0x2420000 0x00 0x400>;
1285 reg = <0x00 0x2430000 0x00 0x400>;
1289 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1297 reg = <0x00 0x2440000 0x00 0x400>;
1309 reg = <0x00 0x2450000 0x00 0x400>;
1313 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1321 reg = <0x00 0x2460000 0x00 0x400>;
1333 reg = <0x00 0x2470000 0x00 0x400>;
1337 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1345 reg = <0x00 0x2480000 0x00 0x400>;
1357 reg = <0x00 0x2490000 0x00 0x400>;
1361 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1369 reg = <0x00 0x24a0000 0x00 0x400>;
1381 reg = <0x00 0x24b0000 0x00 0x400>;
1385 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1393 reg = <0x00 0x24c0000 0x00 0x400>;
1405 reg = <0x00 0x24d0000 0x00 0x400>;
1409 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1417 reg = <0x00 0x24e0000 0x00 0x400>;
1429 reg = <0x00 0x24f0000 0x00 0x400>;
1433 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1441 reg = <0x00 0x2500000 0x00 0x400>;
1453 reg = <0x00 0x2510000 0x00 0x400>;
1457 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1465 reg = <0x00 0x2520000 0x00 0x400>;
1477 reg = <0x00 0x2530000 0x00 0x400>;
1481 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1492 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1493 <0x5d00000 0x00 0x5d00000 0x20000>;
1498 reg = <0x5c00000 0x00010000>,
1499 <0x5c10000 0x00010000>;
1503 ti,sci-proc-ids = <0x06 0xff>;
1513 reg = <0x5d00000 0x00008000>,
1514 <0x5d10000 0x00008000>;
1518 ti,sci-proc-ids = <0x07 0xff>;
1529 reg = <0x0 0x700000 0x0 0x1000>;