Lines Matching +full:driver +full:- +full:strength +full:- +full:ohm
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include "k3-j784s4.dtsi"
16 compatible = "ti,am69-sk", "ti,j784s4";
20 stdout-path = "serial2:115200n8";
36 bootph-all;
42 reserved_memory: reserved-memory {
43 #address-cells = <2>;
44 #size-cells = <2>;
49 no-map;
52 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
53 compatible = "shared-dma-pool";
55 no-map;
58 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
59 compatible = "shared-dma-pool";
61 no-map;
64 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
65 compatible = "shared-dma-pool";
67 no-map;
70 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
71 compatible = "shared-dma-pool";
73 no-map;
76 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
77 compatible = "shared-dma-pool";
79 no-map;
82 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
83 compatible = "shared-dma-pool";
85 no-map;
88 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
89 compatible = "shared-dma-pool";
91 no-map;
94 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
95 compatible = "shared-dma-pool";
97 no-map;
100 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
101 compatible = "shared-dma-pool";
103 no-map;
106 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
107 compatible = "shared-dma-pool";
109 no-map;
112 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
113 compatible = "shared-dma-pool";
115 no-map;
118 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
119 compatible = "shared-dma-pool";
121 no-map;
124 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
125 compatible = "shared-dma-pool";
127 no-map;
130 main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
131 compatible = "shared-dma-pool";
133 no-map;
136 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
137 compatible = "shared-dma-pool";
139 no-map;
142 main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
143 compatible = "shared-dma-pool";
145 no-map;
148 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
149 compatible = "shared-dma-pool";
151 no-map;
154 c71_0_memory_region: c71-memory@a8100000 {
155 compatible = "shared-dma-pool";
157 no-map;
160 c71_1_dma_memory_region: c71-dma-memory@a9000000 {
161 compatible = "shared-dma-pool";
163 no-map;
166 c71_1_memory_region: c71-memory@a9100000 {
167 compatible = "shared-dma-pool";
169 no-map;
172 c71_2_dma_memory_region: c71-dma-memory@aa000000 {
173 compatible = "shared-dma-pool";
175 no-map;
178 c71_2_memory_region: c71-memory@aa100000 {
179 compatible = "shared-dma-pool";
181 no-map;
184 c71_3_dma_memory_region: c71-dma-memory@ab000000 {
185 compatible = "shared-dma-pool";
187 no-map;
190 c71_3_memory_region: c71-memory@ab100000 {
191 compatible = "shared-dma-pool";
193 no-map;
197 vusb_main: regulator-vusb-main5v0 {
199 compatible = "regulator-fixed";
200 regulator-name = "vusb-main5v0";
201 regulator-min-microvolt = <5000000>;
202 regulator-max-microvolt = <5000000>;
203 regulator-always-on;
204 regulator-boot-on;
207 vsys_5v0: regulator-vsys5v0 {
209 compatible = "regulator-fixed";
210 regulator-name = "vsys_5v0";
211 regulator-min-microvolt = <5000000>;
212 regulator-max-microvolt = <5000000>;
213 vin-supply = <&vusb_main>;
214 regulator-always-on;
215 regulator-boot-on;
218 vsys_3v3: regulator-vsys3v3 {
220 compatible = "regulator-fixed";
221 regulator-name = "vsys_3v3";
222 regulator-min-microvolt = <3300000>;
223 regulator-max-microvolt = <3300000>;
224 vin-supply = <&vusb_main>;
225 regulator-always-on;
226 regulator-boot-on;
229 vdd_mmc1: regulator-sd {
231 compatible = "regulator-fixed";
232 regulator-name = "vdd_mmc1";
233 regulator-min-microvolt = <3300000>;
234 regulator-max-microvolt = <3300000>;
235 regulator-boot-on;
236 enable-active-high;
237 vin-supply = <&vsys_3v3>;
241 vdd_sd_dv: regulator-tlv71033 {
243 compatible = "regulator-gpio";
244 regulator-name = "tlv71033";
245 pinctrl-names = "default";
246 pinctrl-0 = <&vdd_sd_dv_pins_default>;
247 regulator-min-microvolt = <1800000>;
248 regulator-max-microvolt = <3300000>;
249 regulator-boot-on;
250 vin-supply = <&vsys_5v0>;
256 dp0_pwr_3v3: regulator-dp0-pwr {
257 compatible = "regulator-fixed";
258 regulator-name = "dp0-pwr";
259 regulator-min-microvolt = <3300000>;
260 regulator-max-microvolt = <3300000>;
261 pinctrl-names = "default";
262 pinctrl-0 = <&dp_pwr_en_pins_default>;
264 enable-active-high;
267 dp0: connector-dp0 {
268 compatible = "dp-connector";
270 type = "full-size";
271 dp-pwr-supply = <&dp0_pwr_3v3>;
275 remote-endpoint = <&dp0_out>;
280 connector-hdmi {
281 compatible = "hdmi-connector";
284 pinctrl-names = "default";
285 pinctrl-0 = <&hdmi_hpd_pins_default>;
286 ddc-i2c-bus = <&mcu_i2c1>;
287 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; /* HDMI_HPD */
291 remote-endpoint = <&tfp410_out>;
296 bridge-dvi {
298 pinctrl-names = "default";
299 pinctrl-0 = <&hdmi_pdn_pins_default>;
300 powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>; /* HDMI_PDn */
304 #address-cells = <1>;
305 #size-cells = <0>;
311 remote-endpoint = <&dpi1_out0>;
312 pclk-sample = <1>;
320 remote-endpoint = <&hdmi_connector_in>;
326 csi_mux: mux-controller {
327 compatible = "gpio-mux";
328 #mux-state-cells = <1>;
329 mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
330 idle-state = <0>;
333 transceiver1: can-phy0 {
335 #phy-cells = <0>;
336 max-bitrate = <5000000>;
339 transceiver2: can-phy1 {
341 #phy-cells = <0>;
342 max-bitrate = <5000000>;
345 transceiver3: can-phy2 {
347 #phy-cells = <0>;
348 max-bitrate = <5000000>;
351 transceiver4: can-phy3 {
353 #phy-cells = <0>;
354 max-bitrate = <5000000>;
360 bootph-all;
361 main_uart8_pins_default: main-uart8-default-pins {
362 bootph-all;
363 pinctrl-single,pins = <
369 main_i2c0_pins_default: main-i2c0-default-pins {
370 pinctrl-single,pins = <
376 main_i2c1_pins_default: main-i2c1-default-pins {
377 pinctrl-single,pins = <
383 main_mmc1_pins_default: main-mmc1-default-pins {
384 bootph-all;
385 pinctrl-single,pins = <
397 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
398 pinctrl-single,pins = <
403 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
404 pinctrl-single,pins = <
422 dp0_pins_default: dp0-default-pins {
423 pinctrl-single,pins = <
428 dp_pwr_en_pins_default: dp-pwr-en-default-pins {
429 pinctrl-single,pins = <
434 dss_vout0_pins_default: dss-vout0-default-pins {
435 pinctrl-single,pins = <
467 hdmi_hpd_pins_default: hdmi-hpd-default-pins {
468 pinctrl-single,pins = <
473 main_mcan6_pins_default: main-mcan6-default-pins {
474 pinctrl-single,pins = <
480 main_mcan7_pins_default: main-mcan7-default-pins {
481 pinctrl-single,pins = <
490 bootph-all;
491 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
492 pinctrl-single,pins = <
509 bootph-all;
510 pmic_irq_pins_default: pmic-irq-default-pins {
511 pinctrl-single,pins = <
517 wkup_uart0_pins_default: wkup-uart0-default-pins {
518 bootph-all;
519 pinctrl-single,pins = <
527 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
528 bootph-all;
529 pinctrl-single,pins = <
535 mcu_uart0_pins_default: mcu-uart0-default-pins {
536 bootph-all;
537 pinctrl-single,pins = <
543 mcu_i2c0_pins_default: mcu-i2c0-default-pins {
544 pinctrl-single,pins = <
550 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
551 pinctrl-single,pins = <
567 mcu_mdio_pins_default: mcu-mdio-default-pins {
568 pinctrl-single,pins = <
574 mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins {
575 pinctrl-single,pins = <
588 mcu_i2c1_pins_default: mcu-i2c1-default-pins {
589 pinctrl-single,pins = <
597 hdmi_pdn_pins_default: hdmi-pdn-default-pins {
598 pinctrl-single,pins = <
603 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
604 pinctrl-single,pins = <
610 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
611 pinctrl-single,pins = <
620 mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins {
621 pinctrl-single,pins = <
630 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
631 ti,mbox-rx = <0 0 0>;
632 ti,mbox-tx = <1 0 0>;
635 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
636 ti,mbox-rx = <2 0 0>;
637 ti,mbox-tx = <3 0 0>;
644 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
645 ti,mbox-rx = <0 0 0>;
646 ti,mbox-tx = <1 0 0>;
649 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
650 ti,mbox-rx = <2 0 0>;
651 ti,mbox-tx = <3 0 0>;
658 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
659 ti,mbox-rx = <0 0 0>;
660 ti,mbox-tx = <1 0 0>;
663 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
664 ti,mbox-rx = <2 0 0>;
665 ti,mbox-tx = <3 0 0>;
672 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
673 ti,mbox-rx = <0 0 0>;
674 ti,mbox-tx = <1 0 0>;
677 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
678 ti,mbox-rx = <2 0 0>;
679 ti,mbox-tx = <3 0 0>;
686 mbox_c71_0: mbox-c71-0 {
687 ti,mbox-rx = <0 0 0>;
688 ti,mbox-tx = <1 0 0>;
691 mbox_c71_1: mbox-c71-1 {
692 ti,mbox-rx = <2 0 0>;
693 ti,mbox-tx = <3 0 0>;
700 mbox_c71_2: mbox-c71-2 {
701 ti,mbox-rx = <0 0 0>;
702 ti,mbox-tx = <1 0 0>;
705 mbox_c71_3: mbox-c71-3 {
706 ti,mbox-rx = <2 0 0>;
707 ti,mbox-tx = <3 0 0>;
714 pinctrl-names = "default";
715 pinctrl-0 = <&wkup_uart0_pins_default>;
719 bootph-all;
721 pinctrl-names = "default";
722 pinctrl-0 = <&wkup_i2c0_pins_default>;
723 clock-frequency = <400000>;
726 /* AT24C512C-MAHM-T */
732 compatible = "ti,tps6594-q1";
734 system-power-controller;
735 pinctrl-names = "default";
736 pinctrl-0 = <&pmic_irq_pins_default>;
737 interrupt-parent = <&wkup_gpio0>;
739 gpio-controller;
740 #gpio-cells = <2>;
741 ti,primary-pmic;
742 buck12-supply = <&vsys_3v3>;
743 buck3-supply = <&vsys_3v3>;
744 buck4-supply = <&vsys_3v3>;
745 buck5-supply = <&vsys_3v3>;
746 ldo1-supply = <&vsys_3v3>;
747 ldo2-supply = <&vsys_3v3>;
748 ldo3-supply = <&vsys_3v3>;
749 ldo4-supply = <&vsys_3v3>;
753 regulator-name = "vdd_ddr_1v1";
754 regulator-min-microvolt = <1100000>;
755 regulator-max-microvolt = <1100000>;
756 regulator-boot-on;
757 regulator-always-on;
761 regulator-name = "vdd_ram_0v85";
762 regulator-min-microvolt = <850000>;
763 regulator-max-microvolt = <850000>;
764 regulator-boot-on;
765 regulator-always-on;
769 regulator-name = "vdd_io_1v8";
770 regulator-min-microvolt = <1800000>;
771 regulator-max-microvolt = <1800000>;
772 regulator-boot-on;
773 regulator-always-on;
777 regulator-name = "vdd_mcu_0v85";
778 regulator-min-microvolt = <850000>;
779 regulator-max-microvolt = <850000>;
780 regulator-boot-on;
781 regulator-always-on;
785 regulator-name = "vdd_mcuio_1v8";
786 regulator-min-microvolt = <1800000>;
787 regulator-max-microvolt = <1800000>;
788 regulator-boot-on;
789 regulator-always-on;
793 regulator-name = "vdd_mcuio_3v3";
794 regulator-min-microvolt = <3300000>;
795 regulator-max-microvolt = <3300000>;
796 regulator-boot-on;
797 regulator-always-on;
801 regulator-name = "vds_dll_0v8";
802 regulator-min-microvolt = <800000>;
803 regulator-max-microvolt = <800000>;
804 regulator-boot-on;
805 regulator-always-on;
809 regulator-name = "vda_mcu_1v8";
810 regulator-min-microvolt = <1800000>;
811 regulator-max-microvolt = <1800000>;
812 regulator-boot-on;
813 regulator-always-on;
821 bootph-pre-ram;
822 regulator-name = "VDD_CPU_AVS";
823 regulator-min-microvolt = <600000>;
824 regulator-max-microvolt = <900000>;
825 regulator-boot-on;
826 regulator-always-on;
832 regulator-name = "VDD_CORE_0V8";
833 regulator-min-microvolt = <760000>;
834 regulator-max-microvolt = <840000>;
835 regulator-boot-on;
836 regulator-always-on;
842 pinctrl-names = "default";
843 pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>;
847 bootph-all;
849 pinctrl-names = "default";
850 pinctrl-0 = <&mcu_uart0_pins_default>;
855 pinctrl-names = "default";
856 pinctrl-0 = <&mcu_i2c0_pins_default>;
857 clock-frequency = <400000>;
861 bootph-all;
863 pinctrl-names = "default";
864 pinctrl-0 = <&main_uart8_pins_default>;
869 pinctrl-names = "default";
870 pinctrl-0 = <&main_i2c0_pins_default>;
871 clock-frequency = <400000>;
876 gpio-controller;
877 #gpio-cells = <2>;
878 gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN",
888 pinctrl-names = "default";
889 pinctrl-0 = <&main_i2c1_pins_default>;
890 clock-frequency = <400000>;
896 gpio-controller;
897 #gpio-cells = <2>;
898 gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz",
902 i2c-mux@70 {
904 #address-cells = <1>;
905 #size-cells = <0>;
909 #address-cells = <1>;
910 #size-cells = <0>;
915 #address-cells = <1>;
916 #size-cells = <0>;
924 bootph-all;
927 non-removable;
928 ti,driver-strength-ohm = <50>;
929 disable-wp;
933 bootph-all;
936 pinctrl-0 = <&main_mmc1_pins_default>;
937 pinctrl-names = "default";
938 disable-wp;
939 vmmc-supply = <&vdd_mmc1>;
940 vqmmc-supply = <&vdd_sd_dv>;
945 pinctrl-names = "default";
946 pinctrl-0 = <&rpi_header_gpio0_pins_default>;
951 pinctrl-names = "default";
952 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
956 mcu_phy0: ethernet-phy@0 {
958 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
959 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
960 ti,min-output-impedance;
966 phy-mode = "rgmii-rxid";
967 phy-handle = <&mcu_phy0>;
972 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
978 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
983 ti,cluster-mode = <0>;
987 ti,cluster-mode = <0>;
1032 ti,cluster-mode = <0>;
1037 memory-region = <&main_r5fss0_core0_dma_memory_region>,
1043 memory-region = <&main_r5fss0_core1_dma_memory_region>,
1049 memory-region = <&main_r5fss1_core0_dma_memory_region>,
1055 memory-region = <&main_r5fss1_core1_dma_memory_region>,
1061 memory-region = <&main_r5fss2_core0_dma_memory_region>,
1067 memory-region = <&main_r5fss2_core1_dma_memory_region>,
1074 memory-region = <&c71_0_dma_memory_region>,
1081 memory-region = <&c71_1_dma_memory_region>,
1088 memory-region = <&c71_2_dma_memory_region>,
1095 memory-region = <&c71_3_dma_memory_region>,
1105 pinctrl-names = "default";
1106 pinctrl-0 = <&mcu_i2c1_pins_default>;
1107 clock-frequency = <100000>;
1112 clock-frequency = <100000000>;
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&dss_vout0_pins_default>;
1119 assigned-clocks = <&k3_clks 218 2>,
1121 assigned-clock-parents = <&k3_clks 218 3>,
1133 cdns,num-lanes = <4>;
1134 #phy-cells = <0>;
1135 cdns,phy-type = <PHY_TYPE_DP>;
1143 pinctrl-names = "default";
1144 pinctrl-0 = <&dp0_pins_default>;
1146 phy-names = "dpphy";
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1158 remote-endpoint = <&dp0_in>;
1167 remote-endpoint = <&tfp410_in>;
1178 remote-endpoint = <&dpi0_out>;
1186 remote-endpoint = <&dp0_connector_in>;
1193 pinctrl-names = "default";
1194 pinctrl-0 = <&mcu_mcan0_pins_default>;
1200 pinctrl-names = "default";
1201 pinctrl-0 = <&mcu_mcan1_pins_default>;
1207 pinctrl-names = "default";
1208 pinctrl-0 = <&main_mcan6_pins_default>;
1214 pinctrl-names = "default";
1215 pinctrl-0 = <&main_mcan7_pins_default>;
1221 pinctrl-names = "default";
1222 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
1225 compatible = "jedec,spi-nor";
1227 spi-tx-bus-width = <8>;
1228 spi-rx-bus-width = <8>;
1229 spi-max-frequency = <25000000>;
1230 cdns,tshsl-ns = <60>;
1231 cdns,tsd2d-ns = <60>;
1232 cdns,tchsh-ns = <60>;
1233 cdns,tslch-ns = <60>;
1234 cdns,read-delay = <4>;
1237 bootph-all;
1238 compatible = "fixed-partitions";
1239 #address-cells = <1>;
1240 #size-cells = <1>;
1253 label = "ospi.u-boot";
1273 bootph-pre-ram;
1282 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
1297 cdns,num-lanes = <3>;
1298 #phy-cells = <0>;
1299 cdns,phy-type = <PHY_TYPE_PCIE>;
1313 cdns,num-lanes = <4>;
1314 #phy-cells = <0>;
1315 cdns,phy-type = <PHY_TYPE_PCIE>;
1322 reset-gpios = <&exp1 4 GPIO_ACTIVE_HIGH>;
1324 phy-names = "pcie-phy";
1329 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
1331 phy-names = "pcie-phy";
1332 num-lanes = <2>;
1337 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
1339 phy-names = "pcie-phy";
1340 num-lanes = <1>;