Lines Matching +full:cache +full:- +full:sets

1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5  * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 		#address-cells = <1>;
13 		#size-cells = <0>;
14 		cpu-map {
37 			compatible = "arm,cortex-a53";
40 			enable-method = "psci";
41 			i-cache-size = <0x8000>;
42 			i-cache-line-size = <64>;
43 			i-cache-sets = <256>;
44 			d-cache-size = <0x8000>;
45 			d-cache-line-size = <64>;
46 			d-cache-sets = <128>;
47 			next-level-cache = <&L2_0>;
51 			compatible = "arm,cortex-a53";
54 			enable-method = "psci";
55 			i-cache-size = <0x8000>;
56 			i-cache-line-size = <64>;
57 			i-cache-sets = <256>;
58 			d-cache-size = <0x8000>;
59 			d-cache-line-size = <64>;
60 			d-cache-sets = <128>;
61 			next-level-cache = <&L2_0>;
65 			compatible = "arm,cortex-a53";
68 			enable-method = "psci";
69 			i-cache-size = <0x8000>;
70 			i-cache-line-size = <64>;
71 			i-cache-sets = <256>;
72 			d-cache-size = <0x8000>;
73 			d-cache-line-size = <64>;
74 			d-cache-sets = <128>;
75 			next-level-cache = <&L2_1>;
79 			compatible = "arm,cortex-a53";
82 			enable-method = "psci";
83 			i-cache-size = <0x8000>;
84 			i-cache-line-size = <64>;
85 			i-cache-sets = <256>;
86 			d-cache-size = <0x8000>;
87 			d-cache-line-size = <64>;
88 			d-cache-sets = <128>;
89 			next-level-cache = <&L2_1>;
93 	L2_0: l2-cache0 {
94 		compatible = "cache";
95 		cache-level = <2>;
96 		cache-unified;
97 		cache-size = <0x80000>;
98 		cache-line-size = <64>;
99 		cache-sets = <512>;
100 		next-level-cache = <&msmc_l3>;
103 	L2_1: l2-cache1 {
104 		compatible = "cache";
105 		cache-level = <2>;
106 		cache-unified;
107 		cache-size = <0x80000>;
108 		cache-line-size = <64>;
109 		cache-sets = <512>;
110 		next-level-cache = <&msmc_l3>;
113 	msmc_l3: l3-cache0 {
114 		compatible = "cache";
115 		cache-level = <3>;
116 		cache-unified;
119 	thermal_zones: thermal-zones {
120 		#include "k3-am654-industrial-thermal.dtsi"