Lines Matching +full:fw +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-pinctrl.h"
17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
18 ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
20 ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
23 /* Ethernet node on PRU-ICSSG0 */
24 icssg0_eth: icssg0-eth {
25 compatible = "ti,am654-icssg-prueth";
26 pinctrl-names = "default";
27 pinctrl-0 = <&icssg0_rgmii_pins_default>;
30 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
31 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
32 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
33 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
34 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
35 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
37 ti,pruss-gp-mux-sel = <2>, /* MII mode */
44 ti,mii-g-rt = <&icssg0_mii_g_rt>;
45 ti,mii-rt = <&icssg0_mii_rt>;
48 interrupt-parent = <&icssg0_intc>;
50 interrupt-names = "tx_ts0", "tx_ts1";
63 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
64 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
67 ethernet-ports {
68 #address-cells = <1>;
69 #size-cells = <0>;
72 phy-handle = <&icssg0_phy0>;
73 phy-mode = "rgmii-id";
74 ti,syscon-rgmii-delay = <&scm_conf 0x4100>;
76 local-mac-address = [00 00 00 00 00 00];
80 phy-handle = <&icssg0_phy1>;
81 phy-mode = "rgmii-id";
82 ti,syscon-rgmii-delay = <&scm_conf 0x4104>;
84 local-mac-address = [00 00 00 00 00 00];
89 /* Ethernet node on PRU-ICSSG1 */
90 icssg1_eth: icssg1-eth {
91 compatible = "ti,am654-icssg-prueth";
92 pinctrl-names = "default";
93 pinctrl-0 = <&icssg1_rgmii_pins_default>;
96 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
97 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
98 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
99 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
100 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
101 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
103 ti,pruss-gp-mux-sel = <2>, /* MII mode */
110 ti,mii-g-rt = <&icssg1_mii_g_rt>;
111 ti,mii-rt = <&icssg1_mii_rt>;
114 interrupt-parent = <&icssg1_intc>;
116 interrupt-names = "tx_ts0", "tx_ts1";
129 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
130 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
133 ethernet-ports {
134 #address-cells = <1>;
135 #size-cells = <0>;
138 phy-handle = <&icssg1_phy0>;
139 phy-mode = "rgmii-id";
140 ti,syscon-rgmii-delay = <&scm_conf 0x4110>;
142 local-mac-address = [00 00 00 00 00 00];
146 phy-handle = <&icssg1_phy1>;
147 phy-mode = "rgmii-id";
148 ti,syscon-rgmii-delay = <&scm_conf 0x4114>;
150 local-mac-address = [00 00 00 00 00 00];
155 transceiver1: can-phy0 {
157 #phy-cells = <0>;
158 max-bitrate = <5000000>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&mcan0_gpio_pins_default>;
161 standby-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>;
164 transceiver2: can-phy1 {
166 #phy-cells = <0>;
167 max-bitrate = <5000000>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&mcan1_gpio_pins_default>;
170 standby-gpios = <&main_gpio1 67 GPIO_ACTIVE_LOW>;
176 icssg0_mdio_pins_default: icssg0-mdio-default-pins {
177 pinctrl-single,pins = <
183 icssg0_rgmii_pins_default: icssg0-rgmii-default-pins {
184 pinctrl-single,pins = <
213 icssg0_iep0_pins_default: icssg0-iep0-default-pins {
214 pinctrl-single,pins = <
219 icssg1_mdio_pins_default: icssg1-mdio-default-pins {
220 pinctrl-single,pins = <
226 icssg1_rgmii_pins_default: icssg1-rgmii-default-pins {
227 pinctrl-single,pins = <
256 icssg1_iep0_pins_default: icssg1-iep0-default-pins {
257 pinctrl-single,pins = <
262 mcan0_gpio_pins_default: mcan0-gpio-default-pins {
263 pinctrl-single,pins = <
268 mcan1_gpio_pins_default: mcan1-gpio-default-pins {
269 pinctrl-single,pins = <
276 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
277 pinctrl-single,pins = <
283 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
284 pinctrl-single,pins = <
293 pinctrl-names = "default";
294 pinctrl-0 = <&icssg0_mdio_pins_default>;
295 #address-cells = <1>;
296 #size-cells = <0>;
298 icssg0_phy0: ethernet-phy@0 {
300 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
301 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
304 icssg0_phy1: ethernet-phy@3 {
306 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
307 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&icssg0_iep0_pins_default>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&icssg1_mdio_pins_default>;
320 #address-cells = <1>;
321 #size-cells = <0>;
323 icssg1_phy0: ethernet-phy@0 {
325 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
326 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
329 icssg1_phy1: ethernet-phy@3 {
331 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
332 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&icssg1_iep0_pins_default>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&mcu_mcan0_pins_default>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&mcu_mcan1_pins_default>;