Lines Matching +full:am654 +full:- +full:icssg
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT overlay for IDK application board on AM654 EVM
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-pinctrl.h"
17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
18 ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
20 ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
23 /* Ethernet node on PRU-ICSSG0 */
24 icssg0_eth: icssg0-eth {
25 compatible = "ti,am654-icssg-prueth";
26 pinctrl-names = "default";
27 pinctrl-0 = <&icssg0_rgmii_pins_default>;
30 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
31 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
32 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
33 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
34 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
35 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
37 ti,pruss-gp-mux-sel = <2>, /* MII mode */
44 ti,mii-g-rt = <&icssg0_mii_g_rt>;
45 ti,mii-rt = <&icssg0_mii_rt>;
46 ti,pa-stats = <&icssg0_pa_stats>;
49 interrupt-parent = <&icssg0_intc>;
51 interrupt-names = "tx_ts0", "tx_ts1";
64 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
65 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
68 ethernet-ports {
69 #address-cells = <1>;
70 #size-cells = <0>;
73 phy-handle = <&icssg0_phy0>;
74 phy-mode = "rgmii-id";
75 ti,syscon-rgmii-delay = <&scm_conf 0x4100>;
77 local-mac-address = [00 00 00 00 00 00];
81 phy-handle = <&icssg0_phy1>;
82 phy-mode = "rgmii-id";
83 ti,syscon-rgmii-delay = <&scm_conf 0x4104>;
85 local-mac-address = [00 00 00 00 00 00];
90 /* Ethernet node on PRU-ICSSG1 */
91 icssg1_eth: icssg1-eth {
92 compatible = "ti,am654-icssg-prueth";
93 pinctrl-names = "default";
94 pinctrl-0 = <&icssg1_rgmii_pins_default>;
97 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
98 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
99 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
100 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
101 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
102 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
104 ti,pruss-gp-mux-sel = <2>, /* MII mode */
111 ti,mii-g-rt = <&icssg1_mii_g_rt>;
112 ti,mii-rt = <&icssg1_mii_rt>;
113 ti,pa-stats = <&icssg1_pa_stats>;
116 interrupt-parent = <&icssg1_intc>;
118 interrupt-names = "tx_ts0", "tx_ts1";
131 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
132 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
135 ethernet-ports {
136 #address-cells = <1>;
137 #size-cells = <0>;
140 phy-handle = <&icssg1_phy0>;
141 phy-mode = "rgmii-id";
142 ti,syscon-rgmii-delay = <&scm_conf 0x4110>;
144 local-mac-address = [00 00 00 00 00 00];
148 phy-handle = <&icssg1_phy1>;
149 phy-mode = "rgmii-id";
150 ti,syscon-rgmii-delay = <&scm_conf 0x4114>;
152 local-mac-address = [00 00 00 00 00 00];
157 transceiver1: can-phy0 {
159 #phy-cells = <0>;
160 max-bitrate = <5000000>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&mcan0_gpio_pins_default>;
163 standby-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>;
166 transceiver2: can-phy1 {
168 #phy-cells = <0>;
169 max-bitrate = <5000000>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&mcan1_gpio_pins_default>;
172 standby-gpios = <&main_gpio1 67 GPIO_ACTIVE_LOW>;
178 icssg0_mdio_pins_default: icssg0-mdio-default-pins {
179 pinctrl-single,pins = <
185 icssg0_rgmii_pins_default: icssg0-rgmii-default-pins {
186 pinctrl-single,pins = <
215 icssg0_iep0_pins_default: icssg0-iep0-default-pins {
216 pinctrl-single,pins = <
221 icssg1_mdio_pins_default: icssg1-mdio-default-pins {
222 pinctrl-single,pins = <
228 icssg1_rgmii_pins_default: icssg1-rgmii-default-pins {
229 pinctrl-single,pins = <
258 icssg1_iep0_pins_default: icssg1-iep0-default-pins {
259 pinctrl-single,pins = <
264 mcan0_gpio_pins_default: mcan0-gpio-default-pins {
265 pinctrl-single,pins = <
270 mcan1_gpio_pins_default: mcan1-gpio-default-pins {
271 pinctrl-single,pins = <
278 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
279 pinctrl-single,pins = <
285 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
286 pinctrl-single,pins = <
295 pinctrl-names = "default";
296 pinctrl-0 = <&icssg0_mdio_pins_default>;
297 #address-cells = <1>;
298 #size-cells = <0>;
300 icssg0_phy0: ethernet-phy@0 {
302 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
303 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
306 icssg0_phy1: ethernet-phy@3 {
308 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
309 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&icssg0_iep0_pins_default>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&icssg1_mdio_pins_default>;
322 #address-cells = <1>;
323 #size-cells = <0>;
325 icssg1_phy0: ethernet-phy@0 {
327 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
328 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
331 icssg1_phy1: ethernet-phy@3 {
333 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
334 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&icssg1_iep0_pins_default>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&mcu_mcan0_pins_default>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&mcu_mcan1_pins_default>;