Lines Matching +full:0 +full:x34000000
12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
50 reg = <0x00 0x01820000 0x00 0x10000>;
51 socionext,synquacer-pre-its = <0x1000000 0x400000>;
59 reg = <0x00 0x700000 0x00 0x1000>;
67 reg = <0x0 0x900000 0x0 0x2000>;
77 mux-controls = <&serdes0_mux 0>;
82 reg = <0x0 0x910000 0x0 0x2000>;
92 mux-controls = <&serdes1_mux 0>;
97 reg = <0x00 0x02800000 0x00 0x100>;
106 reg = <0x00 0x02810000 0x00 0x100>;
115 reg = <0x00 0x02820000 0x00 0x100>;
124 reg = <0x0 0x4e00000 0x0 0x1200>;
128 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
130 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
131 <&main_udmap 0x4003>;
136 reg = <0x0 0x4e10000 0x0 0x7d>;
145 reg = <0x0 0x104200 0x0 0x30>;
148 pinctrl-single,function-mask = <0x0000001ff>;
154 reg = <0x0 0x104280 0x0 0x20>;
157 pinctrl-single,function-mask = <0x0000000f>;
162 reg = <0x0 0x11c000 0x0 0x2e4>;
165 pinctrl-single,function-mask = <0xffffffff>;
170 reg = <0x0 0x11c2e8 0x0 0x24>;
173 pinctrl-single,function-mask = <0xffffffff>;
178 reg = <0x0 0x2000000 0x0 0x100>;
181 #size-cells = <0>;
190 reg = <0x0 0x2010000 0x0 0x100>;
193 #size-cells = <0>;
202 reg = <0x0 0x2020000 0x0 0x100>;
205 #size-cells = <0>;
214 reg = <0x0 0x2030000 0x0 0x100>;
217 #size-cells = <0>;
227 reg = <0x0 0x03100000 0x0 0x60>;
229 clocks = <&k3_clks 39 0>;
236 reg = <0x0 0x2100000 0x0 0x400>;
241 #size-cells = <0>;
242 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
249 reg = <0x0 0x2110000 0x0 0x400>;
254 #size-cells = <0>;
262 reg = <0x0 0x2120000 0x0 0x400>;
267 #size-cells = <0>;
273 reg = <0x0 0x2130000 0x0 0x400>;
278 #size-cells = <0>;
284 reg = <0x0 0x2140000 0x0 0x400>;
289 #size-cells = <0>;
295 reg = <0x00 0x2400000 0x00 0x400>;
297 clocks = <&k3_clks 23 0>;
299 assigned-clocks = <&k3_clks 23 0>;
307 reg = <0x00 0x2410000 0x00 0x400>;
309 clocks = <&k3_clks 24 0>;
311 assigned-clocks = <&k3_clks 24 0>;
319 reg = <0x00 0x2420000 0x00 0x400>;
321 clocks = <&k3_clks 27 0>;
323 assigned-clocks = <&k3_clks 27 0>;
331 reg = <0x00 0x2430000 0x00 0x400>;
333 clocks = <&k3_clks 28 0>;
335 assigned-clocks = <&k3_clks 28 0>;
343 reg = <0x00 0x2440000 0x00 0x400>;
345 clocks = <&k3_clks 29 0>;
347 assigned-clocks = <&k3_clks 29 0>;
355 reg = <0x00 0x2450000 0x00 0x400>;
357 clocks = <&k3_clks 30 0>;
359 assigned-clocks = <&k3_clks 30 0>;
367 reg = <0x00 0x2460000 0x00 0x400>;
369 clocks = <&k3_clks 31 0>;
370 assigned-clocks = <&k3_clks 31 0>;
379 reg = <0x00 0x2470000 0x00 0x400>;
381 clocks = <&k3_clks 32 0>;
383 assigned-clocks = <&k3_clks 32 0>;
391 reg = <0x00 0x2480000 0x00 0x400>;
393 clocks = <&k3_clks 33 0>;
395 assigned-clocks = <&k3_clks 33 0>;
403 reg = <0x00 0x2490000 0x00 0x400>;
405 clocks = <&k3_clks 34 0>;
407 assigned-clocks = <&k3_clks 34 0>;
415 reg = <0x00 0x24a0000 0x00 0x400>;
417 clocks = <&k3_clks 25 0>;
419 assigned-clocks = <&k3_clks 25 0>;
427 reg = <0x00 0x24b0000 0x00 0x400>;
429 clocks = <&k3_clks 26 0>;
431 assigned-clocks = <&k3_clks 26 0>;
439 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
441 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
446 ti,clkbuf-sel = <0x7>;
447 ti,trm-icp = <0x8>;
448 ti,otap-del-sel-legacy = <0x0>;
449 ti,otap-del-sel-mmc-hs = <0x0>;
450 ti,otap-del-sel-ddr52 = <0x5>;
451 ti,otap-del-sel-hs200 = <0x5>;
452 ti,itap-del-sel-ddr52 = <0x0>;
459 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
461 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
464 ti,clkbuf-sel = <0x7>;
465 ti,trm-icp = <0x8>;
466 ti,otap-del-sel-legacy = <0x0>;
467 ti,otap-del-sel-sd-hs = <0x0>;
468 ti,otap-del-sel-sdr12 = <0xf>;
469 ti,otap-del-sel-sdr25 = <0xf>;
470 ti,otap-del-sel-sdr50 = <0x8>;
471 ti,otap-del-sel-sdr104 = <0x7>;
472 ti,otap-del-sel-ddr50 = <0x4>;
473 ti,itap-del-sel-legacy = <0xa>;
474 ti,itap-del-sel-sd-hs = <0x1>;
475 ti,itap-del-sel-sdr12 = <0xa>;
476 ti,itap-del-sel-sdr25 = <0x1>;
483 reg = <0 0x00100000 0 0x1c000>;
486 ranges = <0x0 0x0 0x00100000 0x1c000>;
490 reg = <0x4080 0x4>;
495 mux-reg-masks = <0x0 0x3>; /* lane select */
501 reg = <0x4090 0x4>;
506 mux-reg-masks = <0x0 0x3>; /* lane select */
512 reg = <0x41e0 0x14>;
517 reg = <0x4140 0x18>;
524 reg = <0x0 0x4000000 0x0 0x4000>;
527 ranges = <0x0 0x0 0x4000000 0x20000>;
538 reg = <0x10000 0x10000>;
555 reg = <0x0 0x4100000 0x0 0x54>;
556 syscon-phy-power = <&scm_conf 0x4000>;
557 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
559 #phy-cells = <0>;
564 reg = <0x0 0x4020000 0x0 0x4000>;
567 ranges = <0x0 0x0 0x4020000 0x20000>;
577 reg = <0x10000 0x10000>;
593 reg = <0x0 0x4110000 0x0 0x54>;
594 syscon-phy-power = <&scm_conf 0x4020>;
595 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
597 #phy-cells = <0>;
602 reg = <0x0 0x00a00000 0x0 0x400>;
609 ti,interrupt-ranges = <0 392 32>;
616 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
624 reg = <0x0 0x310e0000 0x0 0x2000>;
631 ti,interrupt-ranges = <0 64 64>,
637 reg = <0x0 0x33d00000 0x0 0x100000>;
641 #interrupt-cells = <0>;
644 ti,interrupt-ranges = <0 0 256>;
651 reg = <0x00 0x32c00000 0x00 0x100000>,
652 <0x00 0x32400000 0x00 0x100000>,
653 <0x00 0x32800000 0x00 0x100000>;
660 reg = <0x00 0x30e00000 0x00 0x1000>;
666 reg = <0x00 0x31f80000 0x00 0x200>;
676 reg = <0x00 0x31f81000 0x00 0x200>;
686 reg = <0x00 0x31f82000 0x00 0x200>;
696 reg = <0x00 0x31f83000 0x00 0x200>;
706 reg = <0x00 0x31f84000 0x00 0x200>;
716 reg = <0x00 0x31f85000 0x00 0x200>;
726 reg = <0x00 0x31f86000 0x00 0x200>;
736 reg = <0x00 0x31f87000 0x00 0x200>;
746 reg = <0x00 0x31f88000 0x00 0x200>;
756 reg = <0x00 0x31f89000 0x00 0x200>;
766 reg = <0x00 0x31f8a000 0x00 0x200>;
776 reg = <0x00 0x31f8b000 0x00 0x200>;
786 reg = <0x0 0x3c000000 0x0 0x400000>,
787 <0x0 0x38000000 0x0 0x400000>,
788 <0x0 0x31120000 0x0 0x100>,
789 <0x0 0x33000000 0x0 0x40000>,
790 <0x0 0x31080000 0x0 0x40000>;
793 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
801 reg = <0x0 0x31150000 0x0 0x100>,
802 <0x0 0x34000000 0x0 0x100000>,
803 <0x0 0x35000000 0x0 0x100000>,
804 <0x0 0x30b00000 0x0 0x10000>,
805 <0x0 0x30c00000 0x0 0x10000>,
806 <0x0 0x30d00000 0x0 0x8000>;
816 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
817 <0xd>; /* TX_CHAN */
818 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
819 <0xa>; /* RX_CHAN */
820 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
825 reg = <0x0 0x310d0000 0x0 0x400>;
835 #clock-cells = <0>;
848 reg = <0x0 0x600000 0x0 0x100>;
856 ti,davinci-gpio-unbanked = <0>;
857 clocks = <&k3_clks 57 0>;
863 reg = <0x0 0x601000 0x0 0x100>;
871 ti,davinci-gpio-unbanked = <0>;
872 clocks = <&k3_clks 58 0>;
878 …reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x…
883 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
884 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
885 ti,syscon-pcie-id = <&scm_conf 0x210>;
886 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
887 bus-range = <0x0 0xff>;
892 msi-map = <0x0 &gic_its 0x0 0x10000>;
899 …reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x…
904 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
905 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
906 ti,syscon-pcie-id = <&scm_conf 0x210>;
907 ti,syscon-pcie-mode = <&scm_conf 0x4070>;
908 bus-range = <0x0 0xff>;
913 msi-map = <0x0 &gic_its 0x10000 0x10000>;
920 reg = <0x0 0x02b00000 0x0 0x2000>,
921 <0x0 0x02b08000 0x0 0x1000>;
927 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
930 clocks = <&k3_clks 104 0>;
938 reg = <0x0 0x02b10000 0x0 0x2000>,
939 <0x0 0x02b18000 0x0 0x1000>;
945 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
948 clocks = <&k3_clks 105 0>;
956 reg = <0x0 0x02b20000 0x0 0x2000>,
957 <0x0 0x02b28000 0x0 0x1000>;
963 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
966 clocks = <&k3_clks 106 0>;
974 reg = <0x0 0x06f03000 0x0 0x400>,
975 <0x0 0x06f03800 0x0 0x40>;
979 ti,camerrx-control = <&scm_conf 0x40c0>;
981 clocks = <&k3_clks 2 0>;
986 #size-cells = <0>;
988 csi2_0: port@0 {
989 reg = <0>;
996 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
997 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
998 <0x0 0x04a06000 0x0 0x1000>, /* vid */
999 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
1000 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
1001 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
1002 <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */
1003 <0x0 0x04a01000 0x0 0x1000>; /* common1 */
1030 #size-cells = <0>;
1036 reg = <0x0 0x7000000 0x0 0x10000>;
1044 reg = <0x0 0x3000000 0x0 0x100>;
1046 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
1054 reg = <0x0 0x3010000 0x0 0x100>;
1056 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
1064 reg = <0x0 0x3020000 0x0 0x100>;
1066 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
1074 reg = <0x0 0x3030000 0x0 0x100>;
1076 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
1084 reg = <0x0 0x3040000 0x0 0x100>;
1086 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
1094 reg = <0x0 0x3050000 0x0 0x100>;
1096 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
1103 reg = <0x00 0xb000000 0x00 0x80000>;
1107 ranges = <0x0 0x00 0xb000000 0x80000>;
1109 icssg0_mem: memories@0 {
1110 reg = <0x0 0x2000>,
1111 <0x2000 0x2000>,
1112 <0x10000 0x10000>;
1119 reg = <0x26000 0x200>;
1122 ranges = <0x0 0x26000 0x2000>;
1126 #size-cells = <0>;
1129 reg = <0x3c>;
1130 #clock-cells = <0>;
1138 reg = <0x30>;
1139 #clock-cells = <0>;
1150 reg = <0x2e000 0x1000>;
1156 reg = <0x2f000 0x1000>;
1162 reg = <0x32000 0x100>;
1167 reg = <0x33000 0x1000>;
1172 reg = <0x2c000 0x1000>;
1177 reg = <0x20000 0x2000>;
1196 reg = <0x34000 0x4000>,
1197 <0x22000 0x100>,
1198 <0x22400 0x100>;
1208 reg = <0x4000 0x2000>,
1209 <0x23000 0x100>,
1210 <0x23400 0x100>;
1220 reg = <0xa000 0x1800>,
1221 <0x25000 0x100>,
1222 <0x25400 0x100>;
1229 reg = <0x38000 0x4000>,
1230 <0x24000 0x100>,
1231 <0x24400 0x100>;
1241 reg = <0x6000 0x2000>,
1242 <0x23800 0x100>,
1243 <0x23c00 0x100>;
1253 reg = <0xc000 0x1800>,
1254 <0x25800 0x100>,
1255 <0x25c00 0x100>;
1262 reg = <0x32400 0x100>;
1266 #size-cells = <0>;
1274 reg = <0x00 0xb100000 0x00 0x80000>;
1278 ranges = <0x0 0x00 0xb100000 0x80000>;
1280 icssg1_mem: memories@0 {
1281 reg = <0x0 0x2000>,
1282 <0x2000 0x2000>,
1283 <0x10000 0x10000>;
1290 reg = <0x26000 0x200>;
1293 ranges = <0x0 0x26000 0x2000>;
1297 #size-cells = <0>;
1300 reg = <0x3c>;
1301 #clock-cells = <0>;
1309 reg = <0x30>;
1310 #clock-cells = <0>;
1321 reg = <0x2e000 0x1000>;
1327 reg = <0x2f000 0x1000>;
1333 reg = <0x32000 0x100>;
1338 reg = <0x33000 0x1000>;
1343 reg = <0x2c000 0x1000>;
1348 reg = <0x20000 0x2000>;
1367 reg = <0x34000 0x4000>,
1368 <0x22000 0x100>,
1369 <0x22400 0x100>;
1379 reg = <0x4000 0x2000>,
1380 <0x23000 0x100>,
1381 <0x23400 0x100>;
1391 reg = <0xa000 0x1800>,
1392 <0x25000 0x100>,
1393 <0x25400 0x100>;
1400 reg = <0x38000 0x4000>,
1401 <0x24000 0x100>,
1402 <0x24400 0x100>;
1412 reg = <0x6000 0x2000>,
1413 <0x23800 0x100>,
1414 <0x23c00 0x100>;
1424 reg = <0xc000 0x1800>,
1425 <0x25800 0x100>,
1426 <0x25c00 0x100>;
1433 reg = <0x32400 0x100>;
1437 #size-cells = <0>;
1445 reg = <0x00 0xb200000 0x00 0x80000>;
1449 ranges = <0x0 0x00 0xb200000 0x80000>;
1451 icssg2_mem: memories@0 {
1452 reg = <0x0 0x2000>,
1453 <0x2000 0x2000>,
1454 <0x10000 0x10000>;
1461 reg = <0x26000 0x200>;
1464 ranges = <0x0 0x26000 0x2000>;
1468 #size-cells = <0>;
1471 reg = <0x3c>;
1472 #clock-cells = <0>;
1480 reg = <0x30>;
1481 #clock-cells = <0>;
1492 reg = <0x2e000 0x1000>;
1498 reg = <0x2f000 0x1000>;
1504 reg = <0x32000 0x100>;
1509 reg = <0x33000 0x1000>;
1514 reg = <0x2c000 0x1000>;
1519 reg = <0x20000 0x2000>;
1538 reg = <0x34000 0x4000>,
1539 <0x22000 0x100>,
1540 <0x22400 0x100>;
1550 reg = <0x4000 0x2000>,
1551 <0x23000 0x100>,
1552 <0x23400 0x100>;
1562 reg = <0xa000 0x1800>,
1563 <0x25000 0x100>,
1564 <0x25400 0x100>;
1571 reg = <0x38000 0x4000>,
1572 <0x24000 0x100>,
1573 <0x24400 0x100>;
1583 reg = <0x6000 0x2000>,
1584 <0x23800 0x100>,
1585 <0x23c00 0x100>;
1595 reg = <0xc000 0x1800>,
1596 <0x25800 0x100>,
1597 <0x25c00 0x100>;
1604 reg = <0x32400 0x100>;
1608 #size-cells = <0>;