Lines Matching +full:0 +full:x100
12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
50 reg = <0x00 0x01820000 0x00 0x10000>;
51 socionext,synquacer-pre-its = <0x1000000 0x400000>;
59 reg = <0x00 0x700000 0x00 0x1000>;
67 reg = <0x0 0x900000 0x0 0x2000>;
77 mux-controls = <&serdes0_mux 0>;
82 reg = <0x0 0x910000 0x0 0x2000>;
92 mux-controls = <&serdes1_mux 0>;
97 reg = <0x00 0x02800000 0x00 0x100>;
106 reg = <0x00 0x02810000 0x00 0x100>;
115 reg = <0x00 0x02820000 0x00 0x100>;
124 reg = <0x0 0x4e00000 0x0 0x1200>;
128 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
130 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
131 <&main_udmap 0x4003>;
136 reg = <0x0 0x4e10000 0x0 0x7d>;
145 reg = <0x0 0x104200 0x0 0x30>;
148 pinctrl-single,function-mask = <0x0000001ff>;
154 reg = <0x0 0x104280 0x0 0x20>;
157 pinctrl-single,function-mask = <0x0000000f>;
162 reg = <0x0 0x11c000 0x0 0x2e4>;
165 pinctrl-single,function-mask = <0xffffffff>;
170 reg = <0x0 0x11c2e8 0x0 0x24>;
173 pinctrl-single,function-mask = <0xffffffff>;
178 reg = <0x0 0x2000000 0x0 0x100>;
181 #size-cells = <0>;
190 reg = <0x0 0x2010000 0x0 0x100>;
193 #size-cells = <0>;
202 reg = <0x0 0x2020000 0x0 0x100>;
205 #size-cells = <0>;
214 reg = <0x0 0x2030000 0x0 0x100>;
217 #size-cells = <0>;
227 reg = <0x0 0x03100000 0x0 0x60>;
229 clocks = <&k3_clks 39 0>;
236 reg = <0x0 0x2100000 0x0 0x400>;
241 #size-cells = <0>;
242 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
249 reg = <0x0 0x2110000 0x0 0x400>;
254 #size-cells = <0>;
262 reg = <0x0 0x2120000 0x0 0x400>;
267 #size-cells = <0>;
273 reg = <0x0 0x2130000 0x0 0x400>;
278 #size-cells = <0>;
284 reg = <0x0 0x2140000 0x0 0x400>;
289 #size-cells = <0>;
295 reg = <0x00 0x2400000 0x00 0x400>;
297 clocks = <&k3_clks 23 0>;
299 assigned-clocks = <&k3_clks 23 0>;
307 reg = <0x00 0x2410000 0x00 0x400>;
309 clocks = <&k3_clks 24 0>;
311 assigned-clocks = <&k3_clks 24 0>;
319 reg = <0x00 0x2420000 0x00 0x400>;
321 clocks = <&k3_clks 27 0>;
323 assigned-clocks = <&k3_clks 27 0>;
331 reg = <0x00 0x2430000 0x00 0x400>;
333 clocks = <&k3_clks 28 0>;
335 assigned-clocks = <&k3_clks 28 0>;
343 reg = <0x00 0x2440000 0x00 0x400>;
345 clocks = <&k3_clks 29 0>;
347 assigned-clocks = <&k3_clks 29 0>;
355 reg = <0x00 0x2450000 0x00 0x400>;
357 clocks = <&k3_clks 30 0>;
359 assigned-clocks = <&k3_clks 30 0>;
367 reg = <0x00 0x2460000 0x00 0x400>;
369 clocks = <&k3_clks 31 0>;
370 assigned-clocks = <&k3_clks 31 0>;
379 reg = <0x00 0x2470000 0x00 0x400>;
381 clocks = <&k3_clks 32 0>;
383 assigned-clocks = <&k3_clks 32 0>;
391 reg = <0x00 0x2480000 0x00 0x400>;
393 clocks = <&k3_clks 33 0>;
395 assigned-clocks = <&k3_clks 33 0>;
403 reg = <0x00 0x2490000 0x00 0x400>;
405 clocks = <&k3_clks 34 0>;
407 assigned-clocks = <&k3_clks 34 0>;
415 reg = <0x00 0x24a0000 0x00 0x400>;
417 clocks = <&k3_clks 25 0>;
419 assigned-clocks = <&k3_clks 25 0>;
427 reg = <0x00 0x24b0000 0x00 0x400>;
429 clocks = <&k3_clks 26 0>;
431 assigned-clocks = <&k3_clks 26 0>;
439 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
441 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
446 ti,clkbuf-sel = <0x7>;
447 ti,trm-icp = <0x8>;
448 ti,otap-del-sel-legacy = <0x0>;
449 ti,otap-del-sel-mmc-hs = <0x0>;
450 ti,otap-del-sel-ddr52 = <0x5>;
451 ti,otap-del-sel-hs200 = <0x5>;
452 ti,itap-del-sel-legacy = <0xa>;
453 ti,itap-del-sel-mmc-hs = <0x1>;
454 ti,itap-del-sel-ddr52 = <0x0>;
461 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
463 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
466 ti,clkbuf-sel = <0x7>;
467 ti,trm-icp = <0x8>;
468 ti,otap-del-sel-legacy = <0x0>;
469 ti,otap-del-sel-sd-hs = <0x0>;
470 ti,otap-del-sel-sdr12 = <0xf>;
471 ti,otap-del-sel-sdr25 = <0xf>;
472 ti,otap-del-sel-sdr50 = <0x8>;
473 ti,otap-del-sel-sdr104 = <0x7>;
474 ti,otap-del-sel-ddr50 = <0x4>;
475 ti,itap-del-sel-legacy = <0xa>;
476 ti,itap-del-sel-sd-hs = <0x1>;
477 ti,itap-del-sel-sdr12 = <0xa>;
478 ti,itap-del-sel-sdr25 = <0x1>;
485 reg = <0 0x00100000 0 0x1c000>;
488 ranges = <0x0 0x0 0x00100000 0x1c000>;
492 reg = <0x4080 0x4>;
497 mux-reg-masks = <0x0 0x3>; /* lane select */
503 reg = <0x4090 0x4>;
508 mux-reg-masks = <0x0 0x3>; /* lane select */
514 reg = <0x41e0 0x14>;
519 reg = <0x4140 0x18>;
526 reg = <0x0 0x4000000 0x0 0x4000>;
529 ranges = <0x0 0x0 0x4000000 0x20000>;
540 reg = <0x10000 0x10000>;
557 reg = <0x0 0x4100000 0x0 0x54>;
558 syscon-phy-power = <&scm_conf 0x4000>;
559 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
561 #phy-cells = <0>;
566 reg = <0x0 0x4020000 0x0 0x4000>;
569 ranges = <0x0 0x0 0x4020000 0x20000>;
579 reg = <0x10000 0x10000>;
595 reg = <0x0 0x4110000 0x0 0x54>;
596 syscon-phy-power = <&scm_conf 0x4020>;
597 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
599 #phy-cells = <0>;
604 reg = <0x0 0x00a00000 0x0 0x400>;
611 ti,interrupt-ranges = <0 392 32>;
618 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
626 reg = <0x0 0x310e0000 0x0 0x2000>;
633 ti,interrupt-ranges = <0 64 64>,
639 reg = <0x0 0x33d00000 0x0 0x100000>;
643 #interrupt-cells = <0>;
646 ti,interrupt-ranges = <0 0 256>;
653 reg = <0x00 0x32c00000 0x00 0x100000>,
654 <0x00 0x32400000 0x00 0x100000>,
655 <0x00 0x32800000 0x00 0x100000>;
663 reg = <0x00 0x30e00000 0x00 0x1000>;
669 reg = <0x00 0x31f80000 0x00 0x200>;
679 reg = <0x00 0x31f81000 0x00 0x200>;
689 reg = <0x00 0x31f82000 0x00 0x200>;
699 reg = <0x00 0x31f83000 0x00 0x200>;
709 reg = <0x00 0x31f84000 0x00 0x200>;
719 reg = <0x00 0x31f85000 0x00 0x200>;
729 reg = <0x00 0x31f86000 0x00 0x200>;
739 reg = <0x00 0x31f87000 0x00 0x200>;
749 reg = <0x00 0x31f88000 0x00 0x200>;
759 reg = <0x00 0x31f89000 0x00 0x200>;
769 reg = <0x00 0x31f8a000 0x00 0x200>;
779 reg = <0x00 0x31f8b000 0x00 0x200>;
789 reg = <0x0 0x3c000000 0x0 0x400000>,
790 <0x0 0x38000000 0x0 0x400000>,
791 <0x0 0x31120000 0x0 0x100>,
792 <0x0 0x33000000 0x0 0x40000>,
793 <0x0 0x31080000 0x0 0x40000>;
796 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
804 reg = <0x0 0x31150000 0x0 0x100>,
805 <0x0 0x34000000 0x0 0x100000>,
806 <0x0 0x35000000 0x0 0x100000>,
807 <0x0 0x30b00000 0x0 0x10000>,
808 <0x0 0x30c00000 0x0 0x10000>,
809 <0x0 0x30d00000 0x0 0x8000>;
819 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
820 <0xd>; /* TX_CHAN */
821 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
822 <0xa>; /* RX_CHAN */
823 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
828 reg = <0x0 0x310d0000 0x0 0x400>;
838 #clock-cells = <0>;
851 reg = <0x0 0x600000 0x0 0x100>;
859 ti,davinci-gpio-unbanked = <0>;
860 clocks = <&k3_clks 57 0>;
866 reg = <0x0 0x601000 0x0 0x100>;
874 ti,davinci-gpio-unbanked = <0>;
875 clocks = <&k3_clks 58 0>;
881 …reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x…
886 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
887 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
888 ti,syscon-pcie-id = <&scm_conf 0x210>;
889 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
890 bus-range = <0x0 0xff>;
895 msi-map = <0x0 &gic_its 0x0 0x10000>;
902 …reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x…
907 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
908 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
909 ti,syscon-pcie-id = <&scm_conf 0x210>;
910 ti,syscon-pcie-mode = <&scm_conf 0x4070>;
911 bus-range = <0x0 0xff>;
916 msi-map = <0x0 &gic_its 0x10000 0x10000>;
923 reg = <0x0 0x02b00000 0x0 0x2000>,
924 <0x0 0x02b08000 0x0 0x1000>;
930 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
933 clocks = <&k3_clks 104 0>;
941 reg = <0x0 0x02b10000 0x0 0x2000>,
942 <0x0 0x02b18000 0x0 0x1000>;
948 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
951 clocks = <&k3_clks 105 0>;
959 reg = <0x0 0x02b20000 0x0 0x2000>,
960 <0x0 0x02b28000 0x0 0x1000>;
966 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
969 clocks = <&k3_clks 106 0>;
977 reg = <0x0 0x06f03000 0x0 0x400>,
978 <0x0 0x06f03800 0x0 0x40>;
982 ti,camerrx-control = <&scm_conf 0x40c0>;
984 clocks = <&k3_clks 2 0>;
989 #size-cells = <0>;
991 csi2_0: port@0 {
992 reg = <0>;
999 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
1000 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
1001 <0x0 0x04a06000 0x0 0x1000>, /* vid */
1002 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
1003 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
1004 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
1005 <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */
1006 <0x0 0x04a01000 0x0 0x1000>; /* common1 */
1033 #size-cells = <0>;
1039 reg = <0x0 0x7000000 0x0 0x10000>;
1047 reg = <0x0 0x3000000 0x0 0x100>;
1049 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
1057 reg = <0x0 0x3010000 0x0 0x100>;
1059 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
1067 reg = <0x0 0x3020000 0x0 0x100>;
1069 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
1077 reg = <0x0 0x3030000 0x0 0x100>;
1079 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
1087 reg = <0x0 0x3040000 0x0 0x100>;
1089 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
1097 reg = <0x0 0x3050000 0x0 0x100>;
1099 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
1106 reg = <0x00 0xb000000 0x00 0x80000>;
1110 ranges = <0x0 0x00 0xb000000 0x80000>;
1112 icssg0_mem: memories@0 {
1113 reg = <0x0 0x2000>,
1114 <0x2000 0x2000>,
1115 <0x10000 0x10000>;
1122 reg = <0x26000 0x200>;
1125 ranges = <0x0 0x26000 0x2000>;
1129 #size-cells = <0>;
1132 reg = <0x3c>;
1133 #clock-cells = <0>;
1141 reg = <0x30>;
1142 #clock-cells = <0>;
1153 reg = <0x2e000 0x1000>;
1159 reg = <0x2f000 0x1000>;
1165 reg = <0x32000 0x100>;
1170 reg = <0x33000 0x1000>;
1175 reg = <0x2c000 0x1000>;
1180 reg = <0x20000 0x2000>;
1199 reg = <0x34000 0x4000>,
1200 <0x22000 0x100>,
1201 <0x22400 0x100>;
1211 reg = <0x4000 0x2000>,
1212 <0x23000 0x100>,
1213 <0x23400 0x100>;
1223 reg = <0xa000 0x1800>,
1224 <0x25000 0x100>,
1225 <0x25400 0x100>;
1232 reg = <0x38000 0x4000>,
1233 <0x24000 0x100>,
1234 <0x24400 0x100>;
1244 reg = <0x6000 0x2000>,
1245 <0x23800 0x100>,
1246 <0x23c00 0x100>;
1256 reg = <0xc000 0x1800>,
1257 <0x25800 0x100>,
1258 <0x25c00 0x100>;
1265 reg = <0x32400 0x100>;
1269 #size-cells = <0>;
1277 reg = <0x00 0xb100000 0x00 0x80000>;
1281 ranges = <0x0 0x00 0xb100000 0x80000>;
1283 icssg1_mem: memories@0 {
1284 reg = <0x0 0x2000>,
1285 <0x2000 0x2000>,
1286 <0x10000 0x10000>;
1293 reg = <0x26000 0x200>;
1296 ranges = <0x0 0x26000 0x2000>;
1300 #size-cells = <0>;
1303 reg = <0x3c>;
1304 #clock-cells = <0>;
1312 reg = <0x30>;
1313 #clock-cells = <0>;
1324 reg = <0x2e000 0x1000>;
1330 reg = <0x2f000 0x1000>;
1336 reg = <0x32000 0x100>;
1341 reg = <0x33000 0x1000>;
1346 reg = <0x2c000 0x1000>;
1351 reg = <0x20000 0x2000>;
1370 reg = <0x34000 0x4000>,
1371 <0x22000 0x100>,
1372 <0x22400 0x100>;
1382 reg = <0x4000 0x2000>,
1383 <0x23000 0x100>,
1384 <0x23400 0x100>;
1394 reg = <0xa000 0x1800>,
1395 <0x25000 0x100>,
1396 <0x25400 0x100>;
1403 reg = <0x38000 0x4000>,
1404 <0x24000 0x100>,
1405 <0x24400 0x100>;
1415 reg = <0x6000 0x2000>,
1416 <0x23800 0x100>,
1417 <0x23c00 0x100>;
1427 reg = <0xc000 0x1800>,
1428 <0x25800 0x100>,
1429 <0x25c00 0x100>;
1436 reg = <0x32400 0x100>;
1440 #size-cells = <0>;
1448 reg = <0x00 0xb200000 0x00 0x80000>;
1452 ranges = <0x0 0x00 0xb200000 0x80000>;
1454 icssg2_mem: memories@0 {
1455 reg = <0x0 0x2000>,
1456 <0x2000 0x2000>,
1457 <0x10000 0x10000>;
1464 reg = <0x26000 0x200>;
1467 ranges = <0x0 0x26000 0x2000>;
1471 #size-cells = <0>;
1474 reg = <0x3c>;
1475 #clock-cells = <0>;
1483 reg = <0x30>;
1484 #clock-cells = <0>;
1495 reg = <0x2e000 0x1000>;
1501 reg = <0x2f000 0x1000>;
1507 reg = <0x32000 0x100>;
1512 reg = <0x33000 0x1000>;
1517 reg = <0x2c000 0x1000>;
1522 reg = <0x20000 0x2000>;
1541 reg = <0x34000 0x4000>,
1542 <0x22000 0x100>,
1543 <0x22400 0x100>;
1553 reg = <0x4000 0x2000>,
1554 <0x23000 0x100>,
1555 <0x23400 0x100>;
1565 reg = <0xa000 0x1800>,
1566 <0x25000 0x100>,
1567 <0x25400 0x100>;
1574 reg = <0x38000 0x4000>,
1575 <0x24000 0x100>,
1576 <0x24400 0x100>;
1586 reg = <0x6000 0x2000>,
1587 <0x23800 0x100>,
1588 <0x23c00 0x100>;
1598 reg = <0xc000 0x1800>,
1599 <0x25800 0x100>,
1600 <0x25c00 0x100>;
1607 reg = <0x32400 0x100>;
1611 #size-cells = <0>;