Lines Matching +full:0 +full:x02d0
45 reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
46 alignment = <0x1000>;
52 reg = <0 0xa0000000 0 0x100000>;
58 reg = <0 0xa0100000 0 0xf00000>;
64 reg = <0 0xa1000000 0 0x100000>;
70 reg = <0 0xa1100000 0 0xf00000>;
75 reg = <0x00 0xa2000000 0x00 0x00200000>;
76 alignment = <0x1000>;
82 reg = <0x00 0xa2200000 0x00 0x1000>;
90 pinctrl-0 = <&leds_pins_default>;
92 led-0 {
138 #clock-cells = <0>;
146 pinctrl-0 = <&icssg0_rgmii_pins_default>;
170 interrupts = <24 0 2>, <25 1 3>;
173 dmas = <&main_udmap 0xc100>, /* egress slice 0 */
174 <&main_udmap 0xc101>, /* egress slice 0 */
175 <&main_udmap 0xc102>, /* egress slice 0 */
176 <&main_udmap 0xc103>, /* egress slice 0 */
177 <&main_udmap 0xc104>, /* egress slice 1 */
178 <&main_udmap 0xc105>, /* egress slice 1 */
179 <&main_udmap 0xc106>, /* egress slice 1 */
180 <&main_udmap 0xc107>, /* egress slice 1 */
181 <&main_udmap 0x4100>, /* ingress slice 0 */
182 <&main_udmap 0x4101>; /* ingress slice 1 */
183 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
184 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
189 #size-cells = <0>;
190 icssg0_emac0: port@0 {
191 reg = <0>;
194 ti,syscon-rgmii-delay = <&scm_conf 0x4100>;
204 ti,syscon-rgmii-delay = <&scm_conf 0x4104>;
217 AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0)
219 AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0)
226 AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7)
233 AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0)
235 AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)
237 AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)
239 AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)
241 AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0)
247 /* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */
248 AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7)
250 AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT, 7)
252 AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 7)
254 AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7)
261 AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7)
263 AM65X_WKUP_IOPAD(0x0028, PIN_OUTPUT, 7)
265 AM65X_WKUP_IOPAD(0x0030, PIN_OUTPUT, 7)
267 AM65X_WKUP_IOPAD(0x0050, PIN_OUTPUT, 7)
274 AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
276 AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0)
278 AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0)
280 AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0)
287 AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)
295 AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
301 AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */
302 AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */
303 AM65X_IOPAD(0x0178, PIN_INPUT, 6) /* (AD22) UART1_CTSn */
304 AM65X_IOPAD(0x017c, PIN_OUTPUT, 6) /* (AC21) UART1_RTSn */
310 AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */
311 AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */
317 AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
318 AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
319 AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
320 AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
321 AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
322 AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
323 AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
324 AM65X_IOPAD(0x02e0, PIN_INPUT_PULLUP, 0) /* (C24) MMC1_SDWP */
330 AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
336 AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
342 AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */
343 AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */
349 AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */
350 AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */
356 AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
357 AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
358 AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
359 AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
360 AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
361 AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
362 AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
363 AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
364 AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
365 AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
366 AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
367 AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
369 AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
370 AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
371 AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
372 AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
373 AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
374 AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
375 AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
376 AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
377 AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
378 AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
379 AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
380 AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
388 AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
389 AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
395 AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
396 AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
409 pinctrl-0 = <&main_uart1_pins_default>;
414 pinctrl-0 = <&main_pcie_enable_pins_default>;
420 pinctrl-0 = <&mcu_i2c0_pins_default>;
425 reg = <0x60>;
439 pinctrl-0 = <&main_i2c0_pins_default>;
444 reg = <0x51>;
449 reg = <0x54>;
457 pinctrl-0 = <&main_i2c1_pins_default>;
464 pinctrl-0 = <&main_i2c2_pins_default>;
471 pinctrl-0 = <&main_i2c3_pins_default>;
475 #size-cells = <0>;
485 pinctrl-0 = <&main_mmc1_pins_default>;
492 pinctrl-0 = <&usb0_pins_default>;
498 pinctrl-0 = <&usb1_pins_default>;
505 #size-cells = <0>;
512 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
514 flash@0 {
516 reg = <0x0>;
531 seboot@0 {
533 reg = <0x0 0x180000>; /* 1.5M */
538 reg = <0x180000 0x200000>; /* 2M */
543 reg = <0x380000 0x300000>; /* 3M */
548 reg = <0x680000 0x20000>; /* 128K */
553 reg = <0x6a0000 0x20000>; /* 128K */
558 reg = <0x6c0000 0x10000>; /* 64K */
563 reg = <0x6d0000 0x7b0000>; /* 7872K */
568 reg = <0xe80000 0x180000>; /* 1.5M */
577 pinctrl-0 = <&minipcie_pins_default>;
580 phys = <&serdes1 PHY_TYPE_PCIE 0>;
590 ti,mbox-tx = <1 0 0>;
591 ti,mbox-rx = <0 0 0>;
600 ti,mbox-tx = <1 0 0>;
601 ti,mbox-rx = <0 0 0>;
624 pinctrl-0 = <&icssg0_mdio_pins_default>;
626 icssg0_eth0_phy: ethernet-phy@0 {
627 reg = <0>;
633 #size-cells = <0>;
635 led@0 {
636 reg = <0>;
662 #size-cells = <0>;
664 led@0 {
665 reg = <0>;
687 ti,cluster-mode = <0>;